A Method to Accelerate UVM Verification Convergence Using Functional Coverage Negative Feedback

Abstract

The invention discloses a method for accelerating UVM closure verification through function coverage rate negative feedback, and belongs to the field of computer-aided design. The method comprises the steps that a function coverage rate detector corresponding to a device under test (DUT) is built in a UVM verification platform, conducts dynamic sampling on the function coverage rate, sorts dynamic sampling information according to specific requirements of the verification platform, extracts valid data information and transmits the valid data information to an excitation generation end; at the excitation generation end, namely sequence of the UVM, the valid data information is received, constrained control is grouped according to the valid data information, a constraint switch is set, and therefore the verification platform conveniently controls the constraint switch and dynamically adjusts constraints used for generating the sequence of the UVM according to the function coverage rate dynamic sampling information. The method reduces the excitation quantity and the verification time required by closure verification in a UVM verification environment, and improves the logical code development and verification efficiency.

Description

technical field [0001] The invention discloses a method for accelerating the convergence of UVM verification, which belongs to the field of computer aided design, in particular to a method for accelerating the convergence of UVM verification by utilizing the negative feedback of function coverage. Background technique [0002] UVM is a verification methodology newly developed in the chip verification industry. Engineers use it to create robust, reusable, interoperable verification components and verification platforms. UVM provides a set of library functions developed based on the SystemVerilog language. Engineers can save themselves the trouble of developing a verification environment from scratch by calling the library. [0003] UVM and System Verilog provide convenience for verifiers to develop an object-oriented verification environment, and also provide convenience for the verification environment to generate controlled random incentives. Controlled random stimuli are...

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Problems solved by technology

[0004] The present invention aims at the deficiencies and problems existing in the prior art, in order to solve the problem of controlled random excitation, generating some repetitive excitation, increasing coverage, and consuming a lot of simulation verification time, and provides a method to accelerate the convergence of UVM verification by using the negative feedback of function coverage Methods

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