Multi-core on-chip communication network realization method based on ring bus

Abstract

Provided is a multi-core on-chip communication network realization method based on a ring bus. The two-channel ring bus based on multiple isomorphic nodes is adopted for an on-chip communication network, and transmission tasks exist in the form of packets. Each node of the ring bus comprises the upper direction, the lower direction, the left direction and the right direction, and two channel interfaces are provided in each direction, wherein the interfaces in the left direction and the right direction serve as a channel of the bus, and the interfaces in the upper direction and the lower direction serve as interconnection interfaces between function modules and the bus. The method has the advantages that through the design of the isomorphic nodes, the expandability and realizability of the ring bus structure are improved, and challenges brought by interconnection of many on-chip modules can be effectively reduced; two directions and one channel are provided in each node, the nodes select the sending direction of the packets to be forwarded according to the congestion of two schemes, and therefore delay of the bus can be reduced, and the band width can be increased.

Description

technical field [0001] The invention relates to a method for implementing an on-chip communication network applied to a digital signal processor, belonging to the technical field of digital signal processors. Background technique [0002] At present, the communication network in the digital signal processor is a data transmission channel between the cores of the digital signal processor in the digital signal processing chip and between other modules inside the chip. Its functions mainly lie in: [0003] 1. Provide physical channels for data communication between units, ensure correct data access between modules, and meet corresponding bandwidth requirements, thereby improving the operating efficiency of the entire processor chip; [0004] 2. Define a complete data communication network interface protocol, through which the interface between communication modules can be standardized, which is beneficial to the interface design and integration of each module in the communicati...

AI Technical Summary

Problems solved by technology

These general-purpose digital signal processor chips all use a communication network based on a master-slave bus structure. In the master-slave bus structure, all modules are divided into two categories, one is the master module, the other is the slave module, and Data access between slave modules is carried out through direct address lines. This structure simplifies the data communication protocol, but it also brings low utilization efficiency and high power consumption caused by too many connections in the communication structure. , layout and wiring is too complex and other issues

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