Method for achieving low-speed digital frequency conversion
A digital frequency conversion, low-speed technology, applied in the field of wireless communication, to achieve the effect of reducing implementation costs and enhancing processing capabilities
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Embodiment 1
[0027] This embodiment provides a method for realizing low-speed digital frequency conversion, the flow chart of the steps is as follows figure 1 shown, including the following steps:
[0028] Step S1, decomposing the sampled data and the associated clock to obtain L-channel data.
[0029] Step S2, the local oscillator signal is decomposed into M channels of signals, and each channel of signal is multiplied with each channel of data, that is, how many channels of data are decomposed into the sampling data and the accompanying channel clock, and the corresponding local oscillator signal is decomposed into how many channels Signal.
[0030] Step S3: Integrating and N-fold decimation filtering are carried out on the results of the multiplication, and output in the form of real part data and imaginary part data, wherein N≥2, M≥2, L≥2, and N=M=L .
[0031] Optionally, the sampling data is a digital signal obtained after analog-to-digital conversion, which is analog data before ...
Embodiment 2
[0051] In this embodiment, a Field Programmable Gate Array (Field Programmable Gate Array, FPGA for short) is used to implement the method in Embodiment 1. M, L and N are all preferably 2. The data Q0 and Q1 of the upper and lower edges obtained from the sampling data in the form of DDR correspond to half the rate of the ADC sampling clock. Direct digital conversion of Q0 and Q1 is under low clock conditions. For digital frequency conversion processing, its structure is as follows figure 2 and image 3 Shown are the processing of real part data and imaginary part data respectively.
[0052] It should be noted, figure 2 Only when the sampling data is input, the accompanying clock ADC_clk / 2 is input, and the accompanying clock ADC_clk / 2 is not input again in the subsequent steps, the DDS signal of the input multiplier, the data_i_0 or data_i_1 of the output multiplier, and the data_i label of the final filtered output The ADC_clk / 2 means that these signals have the clock cha...
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