Safe and stable reset circuit

Abstract

The invention relates to the field of FPGA application and development, and discloses a safe and stable reset circuit. According to the safe and stable reset circuit, after a switch button is pressed, low-level reset signals generated in the time sequence are output to the reset end of an FPGA chip through a reset chip and a peripheral circuit matched with the reset chip. The reset signals are stable and free of noise, and therefore damage to the FPGA chip can be reduced, and chip burnout can be avoided.

Description

technical field [0001] The present invention relates to the field of field-programmable gate array (Field-Programmable Gate Array, hereinafter referred to as FPGA) application development field, in particular, relates to a safe and stable reset circuit. Background technique [0002] FPGA chip is a semi-custom integrated circuit based on hardware description language, which not only solves the shortage of custom circuits, but also overcomes the defect of limited number of original programmable device gate circuits. In the FPGA system development process, after completing the circuit logic program design based on the hardware description language, the circuit logic program can be burned to the FPGA chip for testing through the peripheral circuit that cooperates with the FPGA chip, and finally completes the verification of the functional module. Therefore, FPGA is widely used and is the mainstream technology of modern integrated circuit design verification. [0003] In the per...

AI Technical Summary

Problems solved by technology

The current reset circuit is mostly a simple circuit composed of switch buttons and a small amount of resistors and capacitors. However, due to the extremely high operating speed of the FPGA chip, when the switch button is manually pressed to reset the FPGA chip, many vibrations may occur. Glitch square wave, which damages the internal circuit of the FPGA chip and causes the phenomenon of burning chips

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