Fan-out wafer level chip packaging method

Abstract

The invention provides a fan-out wafer level chip packaging method being characterized by comprising the following steps of packing a chip (8), wires (9), conductive substrates (2) and a support board (1) to form a plastic packaging layer (4) with filler, removing the support board (1), and filling the bottoms of the plastic packaging layer (4) and the conductive substrates (2) with conducting layers (6). The filler in the plastic packaging layer (4) is one or more of phenolic resin and reinforced unsaturated polyester resin. The fan-out wafer level chip packaging method achieves low cost and high precision through removing the support board (1) and wiring again at the bottom layer, and can be applied to various encapsulation modes, meanwhile, the distance between mounted balls can be reduced obviously through the composition of copper in a wire layer , and the entire supporting strength is reinforced.

Description

technical field [0001] The invention relates to the technical field of integrated circuit packaging, in particular to a fan-out wafer-level chip packaging method. Background technique [0002] In the current semiconductor industry, electronic packaging has become an important aspect of industry development. The development of packaging technology for decades has made high-density, small-size packaging requirements become the mainstream direction of packaging. Fan-out WLP is an embedded package processed at the wafer level, and it is also a major advanced packaging process with a large number of I / Os and high integration flexibility. Moreover, it enables vertical and horizontal multi-chip integration in one package without a substrate. As such, fan-out WLP technology is currently being developed into next-generation packaging technologies such as multi-die, low-profile packaging, and 3DSip. With the development of electronic products to be thinner, lighter, higher pin dens...

AI Technical Summary

Problems solved by technology

[0009] In order to overcome the problems of high cost, relatively low I / O terminal density, low strength and single structure in fan-out wafer-level chip packaging in the prior art, the present invention provides a fan-out wafer-level chip packaging The method comprises the steps of: encapsulating the chip 8, the wire 9, the conductive substrate 2 and the carrier 1 with a filler to form a plastic sealing layer 4; removing the carrier 1; filling the bottom of the plastic sealing layer 4 and the conductive substrate 2 with a dielectric Layer 5

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