MPSoC task scheduling, modeling and assessing method under process variations on basis of UPPAAL-SMC

Abstract

The invention discloses an MPSoC task scheduling, modeling and assessing method under process variations on the basis of UPPAAL-SMC. The MPSoC task scheduling, modeling and assessing method includes the following steps: generating a task allocation and scheduling example for a task set according to task scheduling strategy; conducting modeling on tasks, PE and power consumption on the premise of considering process variations to form a task model, a PE model and a power consumption model, and conducting background allocation to perform model transformation on the task allocation and scheduling example by aid of a list scheduling and the branch and cut algorithm; achieving constraint query by aid of stochastic modeling, generating statistic data through UPPAAL-SMC and getting the performance yield of the task allocation and scheduling example; comparing different performance yield of the task allocation and scheduling examples generated by different task scheduling strategies of the same MPSoC framework or different MPSoC frameworks, and assessing the task scheduling strategies to determine the MPSoC framework with superior performance. MPSoC designers can select between TAS strategies and the MPSoC frameworks with help of the MPSoC task scheduling, modeling and assessing method so as to obtain the optimum combination.

Description

technical field [0001] The invention relates to a multi-core system-on-chip task scheduling modeling and evaluation method under process variation, in particular to a UPPAAL-SMC (static model check UPPAAL) task scheduling modeling and evaluation method with process variation MPSoC. Background technique [0002] With the rapid development of science and technology, embedded systems are playing an increasingly important role. The System-on-a-chip (SoC) that has gradually emerged in recent years has been widely used in the field of embedded systems. . People require embedded devices to have more functions and higher performance, and a multi-core system on a chip (Multiprocessor System-on-a-chip, MPSoC) emerges from this. [0003] Process Variation is a natural change in transistor properties (length, width, gate oxide layer thickness, etc.) in the integrated circuit manufacturing process. When the process node is less than 65nm, the impact is more obvious. This has also becom...

AI Technical Summary

Problems solved by technology

Because the existence of process variation brings large changes to the performance and power consumption of MPSoC, when considering the factors of process variation, the traditional worst-time analysis method used to generate feasible solutions is no longer applicable

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