Invalid screening method of memory units

Abstract

The invention provides an invalid screening method of memory units for initial failure problem of a NOR flash memory. The method comprises the following steps; providing negative high voltages (-5-8V) to all word lines of each physical block of the NOR flash memory, sequentially providing positive low voltages (0-1V) to bit lines for reading operation, wherein the negative high voltages of the word lines reduce leak current of normal memory units to the maximum extent, so that the memory units with defects are prominent; comparing the memory unit current (Icell) read by operation with reference unit current (Iref), if Icell is less than Iref, SA outputs logic 0, which represents that the memory unit is under a normal current state; if Icell is greater than Iref, SA outputs logic 1, which represents that the memory units have defects, therefore, abnormal memory units are screened for subsequent redundant replacement or screening, so that the reliability of the product is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for failure screening of storage units. Background technique [0002] Flash memory (Flash Memory) is constantly developing towards a high-integration and high-capacity storage unit, and the probability of introducing defects in the manufacturing process also increases accordingly. At this stage, the reliability test failure statistics of NOR flash memory have found that the most important defect factor causing early failure problems (mainly appearing within 10 erasing / programming cycles) is the interlayer dielectric (ILD loop) defect. [0003] However, in the existing wafer test project, there is a lack of effective screening of defects in the interlayer dielectric region, which will cause burnout between the bit line (BL) via hole and the control gate during subsequent use. , affecting the reliability of the NOR flash memory. [0004] However, if ...

AI Technical Summary

Problems solved by technology

At this stage, the reliability test failure statistics of NOR flash memory have found that the most important defect factor causing early failure problems (mainly appearing within 10 erasing / programming cycles) is the interlayer dielectric (ILD loop) defect

[0003] However, in the existing wafer test project, there is a lack of effective screening of defects in the interlayer dielectric region, which will cause burnout between the bit line (BL) via hole and the control gate during subsequent use. , affecting the reliability of NOR-type flash memory

[0004] However, if 5 to 10 erasing / programming cycles are added to the wafer test during subsequent use, it will take about 5 seconds to perform an erasing / programming cycle for NOR flash memory, which will largely Increase test time, test cost increases

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