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Forming and filling method of trenches

A filling method and trench technology, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., to reduce the possibility, reduce lattice defects, and improve the filling quality

Inactive Publication Date: 2015-04-29
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
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  • Application Information

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Problems solved by technology

However, during the filling process of the trench 16, the epitaxy will extend and grow to the top of the trench 16 during the growth process inside the trench 16, so that there will be a part of the second semiconductor layer on the dielectric layer 15 at the top of the trench 16. 17 grows from the top of trench 16

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  • Forming and filling method of trenches
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  • Forming and filling method of trenches

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Embodiment Construction

[0022] In order to have a more specific understanding of the technical content, characteristics and effects of the present invention, now in conjunction with the illustrated embodiment, the details are as follows:

[0023] The formation and filling method of the groove of the present embodiment, its specific technological process is as follows:

[0024] Step 1, growing the first semiconductor layer 2 and the dielectric layer 15 sequentially on the semiconductor substrate 1, such as Figure 5 shown.

[0025] The semiconductor substrate 1 and the first semiconductor layer 2 are single crystal materials of Si, C, Ge, SiC or SiGe, and the doping types of the semiconductor substrate 1 and the first semiconductor layer 2 are the same (a typical semiconductor substrate 1 is N type silicon substrate, typically the first semiconductor layer 2 is an N-type silicon epitaxial layer), and the carrier concentration of the semiconductor substrate 1 is greater than that of the first semicond...

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Abstract

The invention discloses a forming and filling method of trenches. The forming and filling method comprises the following steps: (1) growing a first semiconductor layer and a medium layer on a semiconductor substrate; (2) etching interiors of the first semiconductor layer and the medium layer to form trenches; (3) transversely etching the side walls of the trenches to ensure that the medium layer at the top of the trench is partially suspended; (4) filling second semiconductor layers of which the doping type is opposite to that of the first semiconductor layer in the trenches by using a selective epitaxy process. According to the forming and filling method, after the trenches are etched, and the side walls of the trenches are transversely etched, the medium layer at the top of the trench is partially suspended, so that when the second semiconductor layer is filled in the trenches by using the selective epitaxy process in the subsequent procedure, the second semiconductor layer can not grow at the top of the medium layer due to blocking of the medium layer at the top of the trench in an initial stage of filling, so that the probability that the second semiconductor layers at the tops of the trenches are mutually folded is greatly reduced, the trench filling quality is improved, and the lattice imperfection inside the trenches is reduced.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to methods for forming and filling trenches. Background technique [0002] VDMOSFET (Vertical Double Diffused MOSFET, vertical double diffused MOS field effect transistor) can reduce the on-resistance by reducing the thickness of the drain drift region, but reducing the thickness of the drain drift region will reduce the breakdown voltage of the device , Therefore, in VDMOS, increasing the breakdown voltage of the device and reducing the on-resistance of the device are a pair of contradictions. [0003] The super junction MOSFET adopts a new voltage-resistant layer structure, using a series of alternately arranged P-type and N-type semiconductor thin layers to deplete the P-type and N-type regions at a lower reverse voltage to achieve mutual charge compensation, so that the P The N-type N-type region can achieve high breakdown voltage under high doping concentration,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/02H01L21/336
Inventor 刘继全
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP