Clock delay method, clock delay device, delay-locked loop and digital clock management unit

Abstract

The invention discloses a clock delay method, a clock delay device, a delay-locked loop and a digital clock management unit. The clock delay method comprises the following steps: step 1: delaying an input clock for Ti by a delay line to obtain an output clock; step 2: comparing the input clock with the output clock, returning to the step 1 to delay the input clock for (Ti+Tx) / 2 by the delay line again if the input clock is lagged behind the output clock, returning to the step 1 to delay the input clock for (Ty+Ti) / 2 by the delay line if the input clock is ahead of the output clock, and until the input clock is aligned with the output clock, outputting the output clock aligned with the input clock. According to the invention, by the technical scheme, a dichotomous successive approximation mode is adopted to realize alignment; N clock periods are required at most; under the condition with larger difference between the input clock and the output clock, a DLL (Dynamic Link Library) locking speed is improved and the working speed of a chip system is improved.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a clock delay method and device, a delay phase-locked loop and a digital clock management unit. Background technique [0002] A digital clock management (DCM) unit exists in a field programmable gate array (FPGA, Field Programmable Gate Array), and mainly provides three functions: clock deskewing, frequency synthesis and phase shifting. The clock skew is implemented by a delay locked loop (DLL, Delayed Loop Lock). [0003] During the transmission process of the input clock (CLKIN), due to the influence of the load capacitance and the clock distribution network, the phases arriving everywhere will be inconsistent, thus forming a skew (Skew). Delay-locked loops can phase-align the input clock and output clock (CLKOUT), eliminating skew. [0004] The principle of the phase alignment of the input clock and the output clock in the existing delay-locked loop is as follows: the ph...

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Problems solved by technology

[0006] The clock delay method, device, delay phase-locked loop and digital clock management unit provided by the present invention solve the problem of how to quickly realize the alignment of the input clock and the output clock in the case of a large difference between the input clock and the output clock

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