Method for reducing electric leakage of trench gate structure semi-floating gate device

Abstract

The invention discloses a method for reducing electric leakage of a trench gate structure semi-floating gate device. The method includes the step of performing oxidation treatment on silicon remaining at the position close to a field oxide layer side wall in a trench gate channel region during trench etching to form a side wall sacrificial oxide layer with an insulating effect, thereby preventing the current from flowing in the direction of the silicon remaining in the side wall, enabling the current to flow in the direction of a trench-shaped channel of the device and reducing the phenomenon of electric leakage between a source region and a drain region. The method for reducing electric leakage of the trench gate structure semi-floating gate device can be integrated with existing processes and is controllable in cost.

Description

technical field [0001] The present invention relates to the technical field of semiconductor memory, and more particularly, relates to a method for reducing electric leakage of semi-floating gate devices with trench gate (Trench Gate) structure by means of oxidation. Background technique [0002] As one of the basic core chips of electronic products, memory is widely used in various electronic products including mobile phones and mobile handheld products. Among them, the semi-floating gate device, as a new type of storage device, can be applied to different integrated circuits. [0003] Semi-floating gate memory can replace a portion of static random access memory (SRAM). Traditional SRAM requires 6 MOSFET transistors to form a storage unit, which has low integration and occupies a large area. The semi-floating gate transistor can form a storage unit with a single transistor, and its storage speed is close to that of a traditional SRAM storage unit composed of 6 transistor...

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Problems solved by technology

[0007] However, although the semi-floating gate device in the above-mentioned invention patent application can increase the channel length through the U-shaped channel, reduce the unit area, and increase the chip density, due to the structure in the process of forming the U-shaped channel, it will cause on-site oxidation. The remaining silicon on the sidewalls of the layer causes some current in the device to flow in the direction of the remaining silicon between the sidewalls, resulting in leakage between the source and drain regions of the device without the application of a gate electrode Phenomenon

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