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Lead frame and chip package thereof

A chip packaging and lead frame technology, which is applied to semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., to achieve the effects of simple and low process, simple structure and low cost

Active Publication Date: 2015-05-06
GREAT TEAM BACKEND FOUNDRY (DONGGUAN) LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Simplify the packaging process

Method used

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  • Lead frame and chip package thereof
  • Lead frame and chip package thereof
  • Lead frame and chip package thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0057] refer to Figure 1 to Figure 4 , a lead frame provided in Embodiment 1 of the present invention includes a first lead frame 10 and a bridge frame 20,

[0058] The first lead frame 10 includes a first chip holder 11, a plurality of first external pins 12 and a first frame 13, the outer ends of the first external pins 12 are connected to the first frame 13, Its inner end is connected to the first chip holder 11, and the first external pin 12 is provided on the top, bottom, left and right of the first chip holder 11, which are 1201, 1202, 1203, 1204 in sequence, so There is a gap 14 between the first external pins 1203 and 1202,

[0059]The bridge frame 20 includes a second chip holder 21, a plurality of second external pins 22 and a second outer frame 23, the outer ends of the second outer pins 22 are connected to the second outer frame 23, and the inner The end is connected with the second chip holder 21, the second external pin 22 is bent into a groove shape, and the ...

Embodiment 2

[0065] The chip package provided in this embodiment is packaged by the lead frame provided in the first embodiment.

[0066] refer to Figure 5 to Figure 8 , a chip package provided in Embodiment 2 of the present invention, comprising:

[0067] The first lead frame 10, the first lead frame 10 includes a first chip holder 11, a plurality of first external pins 12, the inner ends of the first external pins 12 are connected to the first chip holder 11, The first chip holder 11 is provided with first external pins 12 on the top, bottom, left, and right, which are composed of 1201, 1202, 1203, and 1204 in sequence, and the first external pins 1203 and 1202 are arranged between There are vacancies14;

[0068] A bridge frame 20, the bridge frame 20 is stacked on the first lead frame 10, the bridge frame 20 includes a second chip holder 21, a plurality of second external pins 22, and the second external pins 22 The inner end of the pin is connected to the second chip holder 21, the...

Embodiment 3

[0075] The chip package provided in this embodiment is packaged by the lead frame provided in the first embodiment.

[0076] refer to Figure 9 to Figure 12 The main difference between the chip package provided by Embodiment 3 of the present invention and the chip package provided by Embodiment 2 is that the upper surface of the bridge frame 20 leaks outside the encapsulant 50, and this difference is further improved. Heat dissipation of the chip package. Other structures are the same as those in Embodiment 2.

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Abstract

The invention discloses a lead frame and a chip package thereof. The lead frame includes a first lead frame and a bridge frame; the first lead frame includes a first chip carrier, a plurality of first external pins and a first outer frame, wherein the outer ends of the first outer pins are connected with the first outer frame while the inner ends are connected with the first chip carrier; the bridge frame includes a second chip carrier, a plurality of second external pins and a second outer frame, wherein the outer ends of the second outer pins are connected with the second outer frame while the inner ends are connected with the second chip carrier, the second external pins are bent to be groove type, the height of the second outer frame is higher than the height of the second external pins and lower than the height of the second chip carrier, when the bridge frame is overlapped on the first lead frame, the bottoms of the second external pins and the lower surface of the first lead frame are positioned in a same horizontal plane, and a space for sticking a chip is arranged between the first and second chip carriers.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a lead frame and a chip package thereof Background technique [0002] The semiconductor device packaging method is to arrange the chip cut from the wafer on the lead frame and electrically connect the chip to the lead frame, and then cover the chip with the encapsulation gel to prevent the chip from being damaged by the harsh external environment and provide The medium for the electrical connection between the chip and the external circuit. [0003] The current packaging method is to bond the chip on the chip holder of the lead frame through a bonding material, and then electrically connect the chip and the pins by welding gold wires. Due to the existence of the welding wires, the packaging area is large and the packaging volume is large. , the packaging process is complex. Contents of the invention [0004] The object of the present invention is to provide a ...

Claims

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Application Information

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IPC IPC(8): H01L23/495H01L23/31
CPCH01L24/33H01L2224/32245H01L2924/181H01L2924/00012
Inventor 徐振杰曹周
Owner GREAT TEAM BACKEND FOUNDRY (DONGGUAN) LTD
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