Binary capacitor array applied to single-terminal SARADC (Successive Approximation Analog-to-Digital Converter) and redundancy calibrating method of binary capacitor array

Abstract

The invention discloses a redundancy calibrating method for a binary capacitor array applied to a single-terminal SAR ADC (Successive Approximation Analog-to-Digital Converter). The method can be used for calibrating a dynamic error of the binary capacitor array caused by incomplete establishment. According to the method, a redundantly calibrated binary capacitor array, a comparer, an SAR logical control module and an output code computation module are comprised, wherein the redundantly calibrated binary capacitor array comprises a binary capacitor array as well as an addition redundancy capacitor and a subtraction redundancy capacitor. According to the calibration method, a redundancy capacitor is inserted on the basis of a binary capacitor DAC (Digital-to-Analog Converter) array to realize the purpose that multiple digital codes correspond to one ADC analog input; whether an error exists is detected in a redundant bit conversion process; the addition redundancy capacitor or the subtraction redundancy capacitor is operated according to the corresponding situations so as to compensate the generated error.

Description

technical field [0001] The invention relates to a binary capacitance array redundant calibration method applied to a single-end SAR ADC, which belongs to the SAR ADC calibration technology. Background technique [0002] High-precision SAR ADC (Successive Approximation Register-type Analog-to-Digital Converter) has a large equivalent capacitance at the input of the comparator due to its performance limitation due to thermal noise, so the DAC (Digital-to-Analog Converter) requires a large unit capacitance , the settling time is thus limited and difficult to improve. And because large capacitors are prone to incomplete establishment, misjudgment by the comparator will result in dynamic errors, which will affect the overall linearity of the SAR ADC. [0003] Although the traditional non-binary capacitor array can achieve redundant calibration, allowing the existence of dynamic errors caused by incomplete establishment, and improving the speed of SAR ADC, it needs to add many co...

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Problems solved by technology

[0002] High-precision SAR ADC (Successive Approximation Register-type Analog-to-Digital Converter) has a large equivalent capacitance at the input of the comparator due to its performance limitation due to thermal noise, so the DAC (Digital-to-Analog Converter) requires a large unit capacitance , the settling time is thus limited, making it difficult to improve

And because the large capacitor is prone to incomplete establishment, the comparator will misjudge and generate dynamic errors, which will affect the overall linearity of the SAR ADC.

[0003] Although the traditional non-binary capacitor array can achieve redundant calibration, allowing the existence of dynamic errors caused by incomplete establishment, and improving the speed of SAR ADC, it needs to add many conversion cycles, and the non-binary capacitor array needs ROM to record each bit The weight of the weight and the complex calculation of the final output code greatly increase the complexity of the system, and it is difficult to achieve a matching design on the layout of the non-binary capacitor array

In recent years, a binary capacitor array redundancy algorithm with a fully differential structure has been proposed, but its operation cannot be applied to a SAR ADC with a single-ended structure.

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