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A row address decoding circuit

A decoding circuit and row address technology, applied in the field of semiconductor manufacturing, can solve the problems of large charge pump load and large transistor size, and achieve the effects of reducing power consumption, reducing load capacitance and improving integration.

Active Publication Date: 2018-02-09
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, due to the large size of the transistor, the power required for fast pull-up or pull-down of the word line is relatively large. The load will be quite large

Method used

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Embodiment Construction

[0016] The row address decoding circuit of the present invention will be described in more detail below in conjunction with the schematic diagram, wherein a preferred embodiment of the present invention is represented, it should be understood that those skilled in the art can modify the present invention described here, and still realize the advantages of the present invention Effect. Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.

[0017] In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals, such as changin...

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Abstract

The present invention proposes a row address decoding circuit, which uses a higher reading and writing control voltage, so that the first NMOS transistor, the second NMOS transistor, and the PMOS transistor can all transmit higher voltages, which meets the technical requirements. Higher voltage can make the width of the first NMOS transistor, the second NMOS transistor and the PMOS transistor smaller, reduce the load on the charge pump when multiple block selection circuits in the row address decoding circuit switch simultaneously, and make the load capacitance It is greatly reduced, and the power consumption is also greatly reduced; in addition, the area of ​​the row decoding circuit can be greatly saved. The larger the required capacity, the more the area is saved, which is more conducive to improving the integration level.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a row address decoding circuit. Background technique [0002] Fast reading and writing of storage units has always been the pursuit goal of high-speed memory chips (such as flash, etc.). The row address decoding circuit of the storage unit is necessary in the memory circuit, and is used for decoding and gating the row address. The row address decoding circuit will directly affect the reading speed of the memory and the load of the charge pump. [0003] At present, in order to achieve faster decoding and gating effects, the row address decoding circuit requires high-voltage switching. Usually, the voltage of each tube in the row address decoding circuit is usually relatively high to achieve the purpose of fast switching. This is As a result, the entire row address decoding circuit occupies a large area, which does not conform to the development trend of increasing inte...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/08
Inventor 胡剑肖军张勇
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP