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Manufacturing method of shallow groove isolation structure

A technology of isolation structure and manufacturing method is applied in the manufacturing field of shallow trench isolation structure, which can solve problems such as application scope limitation, and achieve the effects of saving manufacturing cost, simplifying process and improving integration degree.

Inactive Publication Date: 2010-12-08
GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] However, in step (5) of the manufacturing method of the above-mentioned STI structure, limited by the step coverage capability of the filling equipment, the aspect ratio cannot exceed a certain limit, and the width of the shallow groove cannot be lower than a certain limit when its own depth is constant. A limit size, when the size of the device is decreasing day by day, the application range of this technology is gradually limited

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  • Manufacturing method of shallow groove isolation structure
  • Manufacturing method of shallow groove isolation structure
  • Manufacturing method of shallow groove isolation structure

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Embodiment Construction

[0028] In order to better understand the technical content of the present invention, specific embodiments are given together with the attached drawings for description as follows.

[0029] figure 2 Shown is a flow chart of a method for fabricating a shallow trench isolation structure in a preferred embodiment of the present invention; Figure 3a-3e shown in figure 2 Schematic diagrams of device structures in each process shown.

[0030] In this embodiment, an STI is formed on a silicon-on-insulator (SOI) structure by implanting oxygen (Separation by Implanted Oxygen, SIMOX) as an example. In practical applications, silicon-on-insulator (SOI) produced by other processes can also be used, such as the Smart Cut method.

[0031] The SOI structure in this embodiment includes a substrate layer 201, an oxide buried layer 202, and a single crystal silicon top layer 203 in sequence, (such as Figure 3a The structure shown) the manufacturing method provided in this embodiment comp...

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Abstract

The invention provides a manufacturing method of a shallow groove isolation structure, which is used for manufacturing the shallow groove isolation structure. A silicon-on-insulator orderly comprises a silicon substrate layer, an oxidation buried layer and a monocrystalline silicon top layer. The manufacturing method of the shallow groove isolation structure comprises the following steps of: depositing a layer of silicon dioxide and silicon nitride on the monocrystalline silicon top layer to serve as a hard screening layer, coating photoresist and exposing for development, etching the hard screening layer by means of dry etching, removing the residual photoresist, and exposing the position on the monocrystalline silicon top layer for manufacturing the shallow groove isolation structure; and performing oxygen ion implantation from upward side of the monocrystalline silicon top layer and annealing at high temperature to form a silicon dioxide isolation zone on the monocrystalline silicon top layer. The manufacturing method of the shallow groove isolation structure provided by the invention is not required to perform silicon dioxide deposition and chemical mechanical polishing to the shallow groove and can improve the component integration level so as to enhance the integration level, simplify the manufacturing flow and reduce the cost.

Description

technical field [0001] The invention relates to a manufacturing method, and in particular to a manufacturing method of shallow trench isolation. Background technique [0002] Shallow trench isolation technology (Shallow Trench Isolation) is a device isolation technology widely used in integrated circuits. Since the isolation structure prepared by the STI process itself has the advantage of occupying a relatively small area, it has gradually become the mainstream device isolation structure used in advanced manufacturing processes. [0003] Figure 1a~1e Shown is the current method for fabricating an STI structure on a device, and the steps of the fabrication method are as follows: [0004] (1) grow pad oxide layer 102 (for silicon oxide) on silicon substrate 101, then deposit hard mask layer 103 (for silicon nitride); ( Figure 1a ) [0005] (2) coating a photoresist 104 on the hard mask layer 103 and exposing and developing; ( Figure 1b ) [0006] (3) etch the device t...

Claims

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Application Information

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IPC IPC(8): H01L21/762
Inventor 李乐
Owner GRACE SEMICON MFG CORP
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