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Method for eliminating silicon substrate defect in STI process

A shallow trench isolation, silicon substrate technology, applied in the manufacturing of electrical components, circuits, semiconductor/solid-state devices, etc., can solve defects, leakage and other problems, and achieve the effect of overcoming cone defects, solving leakage phenomenon, and good isolation effect

Active Publication Date: 2015-06-24
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0008] In view of the above-mentioned shortcoming of the prior art, the object of the present invention is to provide a method for eliminating the silicon substrate defect in the shallow trench isolation process, which is used to solve the taper defect in the shallow trench isolation etching process in the prior art ( Cone defect), thus solving the leakage phenomenon in the shallow trench isolation process

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  • Method for eliminating silicon substrate defect in STI process
  • Method for eliminating silicon substrate defect in STI process
  • Method for eliminating silicon substrate defect in STI process

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Embodiment Construction

[0040] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] see Figures 1 to 13b . It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of ​​the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitra...

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Abstract

The invention provides a method for eliminating a silicon substrate defect in the STI process. The method includes the following steps that a silicon substrate is provided and is sequentially covered with an oxide layer and a silicon nitride layer, wherein the silicon substrate has the defect; the silicon nitride layer is etched until the surface of the oxide layer is exposed, and then a first trough is formed; the oxide layer is etched along the first trough until the silicon substrate is exposed, and then a second trough is formed; the silicon substrate is etched along the first trough and the second trough until the defect is exposed, and then a third trough is formed; the exposed defect is etched along the first trough, the second trough and the third trough and is eliminated; the silicon substrate is etched along the first trough, the second trough and the third trough, and finally etching on an STI area is completed. According to the method, the defect in the silicon substrate is etched independently, so a defect is prevented from being formed in the isolation trough, the electricity leakage phenomenon in the STI process is lightened, and an isolation effect meeting requirements can be achieved.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for eliminating silicon base defects in the shallow trench isolation process. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, semiconductor process technology has entered the deep sub-micron era, chip integration has continued to increase, and the size of components in the chip has therefore continued to shrink. However, no matter how the component size is reduced, each component in the chip must still have proper insulation or isolation to ensure good component performance. When the characteristic line width of components shrinks below 0.25 microns or even enters the nanometer stage, the traditional intrinsic oxidation isolation technology (LOCOS) is replaced by shallow trench isolation technology (STI) because it cannot meet the requirements of device electrical characteristics and small size. STI te...

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Application Information

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IPC IPC(8): H01L21/762H01L21/308
CPCH01L21/76232
Inventor 刘庆修蒋庆红孙奎
Owner SEMICON MFG INT (SHANGHAI) CORP
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