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A Method for Eliminating Defects of Silicon Substrate During Shallow Trench Isolation Etching Process

A technology of shallow trench isolation and etching process, which is applied in the field of eliminating silicon substrate defects in the process of shallow trench isolation, can solve problems such as leakage and defects, and achieve the effects of overcoming cone defects, solving leakage phenomena, and achieving good isolation effects.

Active Publication Date: 2018-01-30
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] In view of the above-mentioned shortcoming of prior art, the object of the present invention is to provide a kind of method for eliminating silicon substrate defect in shallow trench isolation process, be used for solving the taper defect ( Cone defect) problem, so as to solve the leakage phenomenon in the shallow trench isolation process

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  • A Method for Eliminating Defects of Silicon Substrate During Shallow Trench Isolation Etching Process
  • A Method for Eliminating Defects of Silicon Substrate During Shallow Trench Isolation Etching Process
  • A Method for Eliminating Defects of Silicon Substrate During Shallow Trench Isolation Etching Process

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Embodiment Construction

[0040] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] see Figures 1 to 13b . It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of ​​the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitra...

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Abstract

The invention provides a method for eliminating silicon substrate defects in shallow trench isolation etching process, the method comprising the following steps: providing a silicon substrate, the silicon substrate is covered with an oxide layer and a silicon nitride layer in sequence, wherein the silicon substrate Containing defects; etching the silicon nitride layer until the surface of the oxide layer is exposed to form a first trench; etching the oxide layer along the first trench until the silicon substrate is exposed to form a second trench; Etching the silicon substrate along the first trench and the second trench until the defects are exposed to form a third trench; etching the exposed defects along the first trench, the second trench and the third trench and make it cleared; etch the silicon substrate along the first trench, the second trench and the third trench, and finally complete the etching of the shallow trench isolation region. The invention prevents the formation of defects in the isolation trench by individually etching the defects in the silicon substrate, reduces the leakage phenomenon in the shallow trench isolation process, and achieves the required isolation effect.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for eliminating silicon base defects in the shallow trench isolation process. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, semiconductor process technology has entered the deep sub-micron era, chip integration has continued to increase, and the size of components in the chip has therefore continued to shrink. However, no matter how the component size is reduced, each component in the chip must still have proper insulation or isolation to ensure good component performance. When the characteristic line width of components shrinks below 0.25 microns or even enters the nanometer stage, the traditional intrinsic oxidation isolation technology (LOCOS) is replaced by shallow trench isolation technology (STI) because it cannot meet the requirements of device electrical characteristics and small size. STI te...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762H01L21/308
CPCH01L21/76232
Inventor 刘庆修蒋庆红孙奎
Owner SEMICON MFG INT (SHANGHAI) CORP
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