Wear-leveling method for phase change storage system

Abstract

The invention discloses a wear-leveling method for a phase change storage system. The method comprises the steps that an address mapping table, a reserved section table and a register value are read for a current service request, and a target logical segment number LSN and a corresponding physical segment PSN are obtained; whether a request is a read request or a write request is judged; if the request is a read request, data in the PSN is read directly; otherwise, a physical segment PSN to be written is redetermined according to an RSA distribution mechanism. By adopting a Shift-Flip-N-Write algorithm, the data is written in the correct physical segment PSN; finally, whether all the service requests are completed or not is judged; if the service is completed, whether an invalid segment exists in the reserved section table or not is detected, if the invalid segment exists, exchange of a reserved section is conducted. According to the wear-leveling method for the phase change storage system, a write operation of a phase change storage can be balanced, and therefore the service life of the phase change storage is prolonged.

Description

technical field [0001] The invention belongs to the technical field of computers, and relates to a loss equalization method for a phase change storage system. Background technique [0002] In the computer architecture, the processor and the memory are the two cores of the system. In the past few decades, the processor and the memory have been continuously developed and updated. With the processing speed of the processor getting faster and faster, the memory is also constantly developing, especially the capacity of the main memory is getting larger and larger. [0003] Dynamic random access memory (DRAM) is currently the most common storage technology for main memory systems. It has the advantages of fast speed and high reliability. However, because it is a volatile memory, it needs electricity to maintain the data in the storage system, making it The static power consumption is relatively high. With the increasing capacity of the memory, the proportion of the static energy...

AI Technical Summary

Problems solved by technology

Therefore, the write operation and read operation of PRAM are extremely asymmetrical, and its read operation delay is at the same level as that of DRAM, and its power consumption is more dominant than that of DRAM; however, the cost of write operation is very high, and the delay is about 6-10 times that of DRAM. times, the power consumption is about 3-5 times that of DRAM

[0007] 2) The number of write times is limited

At present, the write endurance of phase change memory can reach 10 8 -10 9 times, but with 10 of DRAM and disk 15 There is still a large gap compared with the

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