Wafer-level semiconductor device and manufacturing method thereof
A semiconductor and wafer-level technology, applied in the field of high-power, large-area wafer-level semiconductor devices and their preparation, can solve the problems that cannot be used to produce large-area, high-power LED devices, and achieve simple structure and simple process. Convenient and low-cost effect
Active Publication Date: 2017-10-03
SUZHOU INST OF NANO TECH & NANO BIONICS CHINESE ACEDEMY OF SCI
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Problems solved by technology
like figure 1 As shown, the chip area increases to 500mm 2 When the yield rate has dropped to 2 When the yield rate is only 0.34 / 10,000, it cannot be used to produce large-area, high-power LED device products.
Method used
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preparation example Construction
[0089] As a more specific embodiment of the present invention, refer to image 3 , the preparation method of the wafer-level semiconductor device may also include:
[0090] (1) directly processing the semiconductor material layer to form a plurality of unit cells 2 with set functions, and setting some of all the unit cells 2 in the normal area as normal unit cells, and setting the rest as redundant units unit cell
[0091] (2) All normal unit cells are divided into two or more multi-level unit groups arranged in parallel, any multi-level unit group includes more than two first parallel groups arranged in series, and any first parallel group includes more than two parallel groups normal unit cell set;
[0092] (3) Test the conduction voltage of each multi-level unit group, and select M first parallel groups and N second parallel groups in series from each multi-level unit group to form a series group according to the test results , and make the conduction voltage of each ser...
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The present invention provides a wafer-level semiconductor device and a preparation method thereof. The wafer-level semiconductor device includes a wafer-level substrate; a plurality of series groups formed on the surface of the substrate and arranged in parallel, each series group includes a plurality of parallel groups arranged in series, and each parallel group includes a plurality of parallel groups arranged in parallel unit cells, wherein each unit cell is an independent functional unit formed by processing a semiconductor layer directly grown on the surface of the substrate; and a wire electrically connected to at least two selected parallels in each series group Between groups, the turn-on voltages of all series groups are basically the same. The device of the invention has simple structure, simple and convenient manufacturing process, low cost and high yield, and is suitable for large-scale manufacturing and application.
Description
technical field [0001] The invention relates to a semiconductor device and its preparation process, in particular to a high-power, large-area wafer-level semiconductor device and its preparation method. The wafer-level semiconductor device is a plurality of unit cells formed on a wafer. Devices connected in series and parallel can be used without cutting and separating. Background technique [0002] In recent years, people have put forward higher and higher requirements for the power of LED lighting. In order to obtain a high-power light source, the current industry usually integrates multiple small-sized LED chips made by traditional processes into one device. As one of the typical solutions, referring to CN103137643A, CN103107250A, etc., \personnel fix and assemble a plurality of small-sized LED chips on a substrate by bonding, etc., and use a certain circuit form to electrically connect the plurality of LED chips. Sexual connection, thus forming a high-power LED device....
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IPC IPC(8): H01L27/15H01L33/00
Inventor 蔡勇张亦斌徐飞
Owner SUZHOU INST OF NANO TECH & NANO BIONICS CHINESE ACEDEMY OF SCI