Semiconductor device preparation method

Abstract

The invention provides a semiconductor device preparation method, at least comprising the steps of: successively depositing a pad oxide layer and a pad nitride layer on the active area (AA) surface of a semiconductor substrate and etching the pad oxide layer, the pad nitride layer and AAs to form a groove for separating adjacent AAs; employing the etching technology to etch part of the pad oxide layer and the pad nitride layer close to the groove by a preset thickness to expose part of the AA surface; filling insulating materials in the groove to form a shallow channel isolation structure; removing the pad oxide layer and the pad nitride layer on two sides of the shallow channel isolation structure to expose the AA surface on two sides of the shallow channel isolation structure and grow gate oxide on the AA surface; and depositing to form floating gates on a gate oxide surface. In the preparation method, the sidewalls of the pad oxide layer and the pad nitride layer are etched by a certain thickness before filling the insulating materials, allowing the insulating materials subsequently filled in the groove to cover the AA surface, guaranteeing corners of the AA surface to be covered by insulating materials thick enough, and avoiding sharp corner effects.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing, and relates to a method for preparing a semiconductor device. Background technique [0002] With the development of semiconductor technology, the feature size of devices in integrated circuits has become smaller and smaller, and the speed of devices and systems has increased accordingly. After the semiconductor process enters the deep submicron stage, in order to realize high-density, high-performance devices and circuits, the isolation and planarization process becomes more and more important. [0003] At present, methods for forming isolation regions mainly include local oxidation isolation process (LOCOS) or shallow trench isolation process (STI). [0004] The LOCOS process is to deposit a layer of silicon oxide on the surface of the wafer, and then perform etching to oxidize and grow silicon oxide in part of the recessed area, and the active device is generated in the area d...

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Problems solved by technology

[0009] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for manufacturing a semiconductor device, which is used to solve the problem of sharp corners at the corners of the active region of the shallow trench isolation structure in the prior art, resulting in large leakage currents. The problem

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