Semiconductor device and method for adaptive patterning of board packaging
A semiconductor and pattern technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of reducing packaging quality and reliability, increasing packaging yield loss, etc.
Active Publication Date: 2018-06-26
DECA TECH USA INC
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- Application Information
AI Technical Summary
Problems solved by technology
Displacement of the semiconductor chip, including rotation of the semiconductor chip, may result in a defective semiconductor package that reduces package quality and reliability and also increases package yield loss
Method used
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Embodiment Construction
[0042] Embodiments of the present disclosure disclose methods and systems for improving board packaging. According to an embodiment of the present disclosure, the misalignment of individual device units in a panel or mesh wafer can be adjusted by measuring the misalignment of each individual device unit and using maskless patterning techniques to adjust The location or design of features in the build-up layers for each respective device unit is adjusted.
[0043] In the following description, numerous specific details are set forth, such as particular configurations, compositions, processes, etc., in order to provide a thorough understanding of the present disclosure. In other instances, well known processes and fabrication techniques have not been described in particular detail in order not to unnecessarily obscure the present disclosure. Furthermore, the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
[004...
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The present invention describes an adaptive patterning method and system for fabricating panel-based packaging structures. A plurality of semiconductor chips are provided, the semiconductor chips including copper pillars disposed over the active surface of each semiconductor chip. An embedded chip panel is formed by disposing an encapsulant around each of the plurality of semiconductor chips. Measure the true position and rotation of each semiconductor chip within the embedded chip panel. Cell specific patterns are formed to align with the true position of each semiconductor chip in the embedded chip panel. The cell specific pattern is arranged as a fan-out structure over the semiconductor chip, over the encapsulant and coupled to the copper pillars. A fan-in redistribution layer (RDL) may extend over the active surface of each semiconductor chip such that the copper pillars are formed over the fan-in RDL. The cell specific pattern can be directly coupled to the copper pillar.
Description
technical field [0001] The present disclosure relates generally to semiconductor devices, and more particularly to adaptive patterning in the field of panel packaging for forming fan-out wafer-level packaging (FOWLP). Background technique [0002] Semiconductor devices are ubiquitous in modern electronics. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices typically contain one type of electrical component, such as light emitting diodes (LEDs), small signal transistors, resistors, capacitors, inductors, and power metal oxide semiconductor field effect transistors (MOSFETs). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charge-coupled devices (CCDs), solar cells, and digital micromirror devices (DMDs). [0003] Semiconductor devices perform a wide range of functions, such as si...
Claims
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IPC IPC(8): H01L21/98
CPCH01L21/561H01L21/565H01L21/568H01L23/3128H01L24/19H01L24/20H01L24/96H01L24/97H01L2224/12105H01L2224/73267H01L2224/97H01L2924/01322H01L2924/12041H01L2924/1306H01L2924/13091H01L2924/181H01L2924/18162H01L2924/00H01L2224/82H01L2224/83H01L2224/82103H01L2224/94H01L2924/00012H01L2224/03
Inventor C.M.斯坎伦T.L.奥尔森
Owner DECA TECH USA INC