Flip Chip Stacked Package

Abstract

The present invention provides the flip chip stacked package, an intermediary layer is applied to the flip chip stacked package to connect a first chip and a second chip, and comprises a first jointing surface and a corresponding second jointing surface; a plurality of conductive penetrating holes penetrating the first and second jointing surfaces; a first radiating metal layer configured on the first jointing surface; a second radiating metal layer configured on the second jointing surface, wherein the first and second radiating metal layers are in electrical isolation with the conductive penetrating holes, and between the adjacent conductive penetrating holes, the first radiating metal layer is arranged on the first jointing surface, and the second radiating metal layer is arranged on the second jointing surface. The first chip is configured on the first jointing surface, the second chip is configured on the second jointing surface, and the first and second chips are connected electrically via the conductive penetrating holes.

Description

technical field [0001] The present invention relates to a stacked package, and in particular to a flip-chip stacked package that can improve heat dissipation. Background technique [0002] With the thinning and thinning of electronic products, the integration level of semiconductor chips and the demand for high-density semiconductor packaging also increase accordingly. Stacked chip semiconductor package (stacked chip package), system-in-package (system in package), can accommodate multiple chips in one package to increase packaging density, so it has been widely used in many electronic products in recent years. In the semiconductor packaging technology, the flip chip technology (flip chip) allows the contacts of the chip to be arranged in an array, and provides an excellent bonding method between the chip and the packaging substrate for a high-pin count chip. These highly integrated chips and high-density packaging structures will generate relatively more heat energy during...

AI Technical Summary

Problems solved by technology

[0003] The heat dissipation method of the known semiconductor package usually adds a heat sink outside the package, such as a heat dissipation metal sheet arranged outside the package to meet the heat dissipation requirements. However, when this heat dissipation method is applied to the package structure of stacked chips, the bottom layer The heat dissipation efficiency of the chip is poorer than that of the top chip

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