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Power consumption optimizing method for RM (Reed-Muller) logical circuit comprising irrelevant items

A logic circuit and optimization method technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve the problem of RM logic circuit power consumption optimization, etc., to achieve obvious advantages, speed up the convergence speed, and reduce the search space Effect

Active Publication Date: 2015-09-02
BEIHANG UNIV
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Problems solved by technology

[0011] The purpose of the present invention is to solve the problem that the power consumption optimization of the RM logic circuit containing irrelevant items is insufficient at present, and proposes a method for optimizing the power consumption of the RM logic circuits containing irrelevant items

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  • Power consumption optimizing method for RM (Reed-Muller) logical circuit comprising irrelevant items
  • Power consumption optimizing method for RM (Reed-Muller) logical circuit comprising irrelevant items
  • Power consumption optimizing method for RM (Reed-Muller) logical circuit comprising irrelevant items

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Embodiment Construction

[0042] according to figure 1 , figure 2 and image 3 Shown, the specific embodiment of the present invention is as follows:

[0043] In the present invention, the RM logic circuit power consumption optimization comprising irrelevant items is mainly composed of figure 1 and figure 2 The two-part algorithm shown is Algorithm 1 and Algorithm 2, figure 1 In order to use the improved adaptive genetic algorithm to solve the optimal polarity switching order of the polarity set to be evaluated in each generation, figure 2 Optimal polarity for searching RM logic circuits containing irrelevant terms;

[0044] in, figure 1 and figure 2 The main implementation steps of the shown algorithm are as follows:

[0045] Step 1: Realize the polarity conversion from a Boolean logic circuit containing irrelevant items to an RM logic circuit;

[0046] Step 2: Generate randomly figure 2 The initial population of genetic algorithm in, wherein, described initial population is the polarit...

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Abstract

The invention relates to a power consumption optimizing method for an RM (Reed-Muller) logical circuit comprising irrelevant items. The method comprises steps as follows: 1, polarity conversion from irrelevant-item-containing Boolean logic to RM logic is realized; 2, initial population is generated randomly; 3, conversion of decimal polarity to a binary system or a ternary system is completed; 4, different digits among different polarities in a polar set of the population are calculated; 5, the best polarity conversion sequence in each generation of to-be-evaluated polar set is calculated with an improved self-adaption genetic algorithm; 6, polarity conversion is performed on the current polar set according to the sequence obtained in the step 5; 7, the fitness value of each polarity is calculated according to an RM expression and a fitness function of the corresponding polarity, and an elitism preservation strategy is executed; 8, if current evolutionary algebra is smaller than the largest iteration times, steps 9 and 10 are executed, and otherwise, the best polarity is output; 9, selection, intercrossing and mutation operation are executed; 10, operations from the step 4 to the step 7 are circularly executed. The polarity searching efficiency is improved, and the convergence and the robustness of the genetic algorithm are enhanced.

Description

technical field [0001] The invention relates to a method for optimizing the polarity of a Reed-Muller logic circuit, in particular to a method for optimizing power consumption of a Reed-Muller logic circuit including irrelevant items. The invention belongs to the technical field of integrated circuit optimization design. Background technique [0002] With the rapid development of integrated circuits, the complexity of their design is also increasing, the traditional manual design method has long been invalid, computer-aided design (CAD) and electronic design automation (EDA) came into being. When CAD tools optimize circuit design in different design abstraction layers, logic-level circuit optimization is one of the key components of integrated circuit optimization design. The logic-level automation design of integrated circuits plays an important role in the performance optimization of the circuit's power consumption and area. [0003] At present, the optimal design of int...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 王翔张荣王维克何振学沈全能周成
Owner BEIHANG UNIV
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