Capacitance mismatch calibrating circuit and calibrating method applied to single-end SAR ADC

Abstract

The invention discloses a capacitance mismatch calibrating circuit and calibrating method applied to a single-end SAR ADC (Successive Approximation Analog-to-Digital Converter). By using the method, error caused by capacitance mismatch of the SAR ADC can be calibrated. According to the method, only two pairs of redundant capacitance need to be inserted in an analog domain for compensation of capacitance mismatch in a digital domain. A binary capacitance DAC (Digital-to-Analog Converter) containing two pairs of redundant dot capacitance includes a segmentation binary capacitance DAC and redundant capacitance Cjr+, Cjr- inserted to the lowest bit of aN MSB segment of a segmentation capacitance, and redundant capacitance Cqr+, Cqr- inserted to an LSB segment. A redundant bit calculation module adds the inserted redundant bits to other normal bits and obtains N-bit valid output. A capacitance mismatch calibrating module performs compensation to capacitance mismatch on the output result. Compared with the traditional SAR ADC structure, only two pairs of redundant capacitance are added. The calculation of mismatch compensation is performed in the digital domain, so that the layout size and analog circuit complexity is reduced.

Description

technical field [0001] The invention relates to a mismatch calibration method applied to a single-end SAR ADC capacitance, which belongs to the SAR ADC calibration technology. Background technique [0002] High-precision SAR ADC (Successive Approximation Register-type Analog-to-Digital Converter) needs to use larger capacitors to meet the requirements of capacitor matching due to the limitation of its capacitor mismatch, especially when the accuracy is higher than 12-bit. Capacitor mismatch calibration is required to address the effects of capacitor mismatch. However, with large DAC (digital-to-analog converter) capacitors, settling time is thus limited and power consumption increases. In addition, the traditional calibration method requires a separate calibration DAC array for each capacitor that needs to be calibrated. Although the calibration DAC array only needs about 5 bits, once there are many capacitors that need to be calibrated, the capacitance of the calibration D...

AI Technical Summary

Problems solved by technology

However, with large DAC (digital-to-analog converter) capacitors, settling time is limited and power consumption increases

In addition, the traditional calibration method requires a separate calibration DAC array for each capacitor that needs to be calibrated. Although the calibration DAC array only needs about 5 bits, once there are many capacitors that need to be calibrated, the capacitance of the calibration DAC array may be different from that of the DAC itself. The area occupied by the array is equivalent, which directly leads to the increase of chip cost

[0003] Although the non-binary capacitance DAC arrays in recent years can realize capacitance mismatch calibration, due to the use of non-binary capacitance DAC arrays, the matching degree of its layout will be significantly worse than that of binary capacitance DAC arrays, and in digital logic, due to the need to store each The weight of each capacitor, its complexity is also increased a lot

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