Configurable fractional frequency divider

Abstract

The invention relates to a configurable fractional frequency divider which comprises a rising edge reference clock selection circuit, a falling edge reference clock selection circuit, a low level control circuit, a high level control circuit, a state selection circuit and an output circuit, wherein the rising edge reference clock selection circuit and the falling edge reference clock selection circuit have the same circuit structure; and the low level control circuit and the high level control circuit have the same circuit structure. The configurable fractional frequency divider receives L input clocks CLKMP, controls the edge inverting moment and the high-low level duration time of the output clocks through a configuration signal, and generates an output clock CLKOUT with the required frequency, wherein the CLKMP needs to meet the requirement that the frequency is the same and the phase difference is 360 degrees / L. The configurable fractional frequency divider is realized by using an adder, the subtraction counter and simple control logic, the circuit complexity is low, and the area and the power consumption required by the circuit are reduced.

Description

technical field [0001] The invention relates to a configurable fractional frequency divider, in particular to a configurable fractional frequency divider for multi-phase clock input, and belongs to the technical field of integrated circuits. Background technique [0002] In circuit design, a frequency divider is usually used to generate another low-frequency output clock from a high-frequency input clock to meet the frequency requirements of different units in the circuit for the clock. Frequency dividers are generally divided into integer frequency dividers and fractional frequency dividers. The integer frequency divider can generally be realized through the counter, and the realization method is simple. [0003] The fractional frequency divider usually uses Σ-Δ modulation to control the integer frequency division, so that the average value of the integer frequency division reaches the fractional frequency division target, thereby realizing the fractional frequency divisio...

AI Technical Summary

Problems solved by technology

However, the circuit structure of the fractional frequency divider designed with Σ-Δ modulation is relatively complex, the required circuit area and power consumption are large, the frequency division value is unique, and the suppression of quantization noise needs to be considered

Images