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A differential pair input circuit with constant transconductance

An input circuit and differential input technology, applied in differential amplifiers, DC-coupled DC amplifiers, improved amplifiers to reduce temperature/power supply voltage changes, etc., can solve the problem of large drain-source voltage, increased circuit design complexity, and uneven bias voltage. Reconciliation and other issues to achieve the effect of reducing the impact

Active Publication Date: 2018-10-16
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This pair of contradictions is not easy to reconcile. In some circuit analysis, it often occurs that the drain-source voltage of the switch tube is too large when it is turned on, causing the tail current source tube to be in the linear region.
On the other hand, the 3 times current mirror constant transconductance circuit requires accurate bias voltage VBIASN, VBIASP, such as figure 2 As shown, this increases the design complexity of the circuit; at the same time, under some extreme circuit technology, environment, and power supply conditions, the generated bias voltage is likely to no longer meet the circuit requirements

Method used

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  • A differential pair input circuit with constant transconductance
  • A differential pair input circuit with constant transconductance
  • A differential pair input circuit with constant transconductance

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Embodiment Construction

[0047] The implementation of the present invention is described below through specific examples and in conjunction with the accompanying drawings, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0048] The present invention is to traditional 3 times current mirror structure (such as figure 1 shown) was modified, as in image 3 Shown is the structural block diagram of the present invention. The NMOS differential input pair is NM1 and NM2 tubes; the PMOS differential input pair is PM1 and PM2 tubes; the tail current source values ​​are all I 0 . By monitoring the voltage of nodes ...

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Abstract

The invention discloses a novel transconductance constant differential pair input circuit comprising an NMOS differential input pair and a PMOS differential input pair. Tail current values of the NMOS differential input pair and the PMOS differential input pair are both I; the differential pair input circuit controls on-off current source of a 3-times tail current source switch tube via monitoring voltage of an intermediate node (A) of the PMOS differential input pair and an intermediate node (B) of the NMOS differential input pair and voltage value fluctuation; and the current source is connected to one part of the differential input pair and working as the tail current. With monitoring voltages of the nodes (A,B), the 3-times tail current source switch tube bias voltage fluctuates to a proper value to control on-off of the switch tube to control changes of the differential pair tail currents; and transconductance input and constant can be achieved.

Description

technical field [0001] The invention relates to the field of CMOS analog circuit design, in particular to a differential pair input circuit with constant transconductance. Background technique [0002] In the rail-to-rail operational amplifier (Rail-to-RailOPAMP) design, the input stage is required to have a constant transconductance function (constant transconductance) from the low potential of the power supply to the high potential, that is, within the rail-to-rail voltage range ). A single PMOS or NMOS differential input pair will be in the cut-off, sub-threshold, linear and saturated four operating regions in the full voltage range, and its transconductance changes from zero to the maximum value. [0003] Since the PMOS transistor is turned on at a low gate voltage, it is turned off at a high gate voltage; while the NMOS transistor is just the opposite, it is turned off at a low gate voltage and turned on at a high gate voltage. According to this characteristic, when t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03F1/30H03F3/45
Inventor 谢加雄张宁蔡俊
Owner SHANGHAI HUALI MICROELECTRONICS CORP