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High-voltage CMOS integrated structure and manufacture method thereof

A manufacturing method and technology of the manufacturing method, which are applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of high manufacturing cost and high cost of high-voltage CMOS integrated structures, and achieve the effect of reducing manufacturing and process costs.

Active Publication Date: 2015-10-14
FOUNDER MICROELECTRONICS INT
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Problems solved by technology

[0003] However, because the integration of high-voltage NMOS and high-voltage PMOS and the isolation region are all fabricated in the epitaxial layer, and the fabrication of the epitaxial layer requires expensive semiconductor materials, it leads to the problem of high fabrication cost of the high-voltage CMOS integrated structure

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  • High-voltage CMOS integrated structure and manufacture method thereof
  • High-voltage CMOS integrated structure and manufacture method thereof
  • High-voltage CMOS integrated structure and manufacture method thereof

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Embodiment Construction

[0018] figure 2 It is a structural schematic diagram of Embodiment 1 of the high-voltage CMOS integrated structure of the present invention, as figure 2 As shown, the high-voltage CMOS integrated structure includes: a P-type substrate, a high-voltage PMOS, a non-isolated high-voltage NMOS, an isolated high-voltage NMOS, and an isolation region. The high-voltage PMOS, the non-isolated high-voltage NMOS, the isolated high-voltage NMOS, and the isolation region are respectively arranged in the P-type substrate, and the isolation region is arranged between the non-isolated high-voltage NMOS and the isolated between high voltage NMOS.

[0019] In this embodiment, the CMOS is a combined structure in which an N-channel Metal Oxide Semiconductor Field Effect Transistor (MOS for short) and a P-channel MOS (PMOS for short) are electrically connected in a certain manner. The high-voltage CMOS integrated structure usually includes at least three high-voltage MOS devices: non-isolated ...

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Abstract

The invention provides a high-voltage CMOS integrated structure and a manufacture method thereof. The high-voltage CMOS integrated structure comprises a P-type substrate, a high-voltage PMOS, a non-isolated high-voltage NMOS, an isolated high-voltage NMOS and an isolation region. The high-voltage PMOS, the non-isolated high-voltage NMOS, the isolated high-voltage NMOS and the isolation region are arranged in the P-type substrate; and the isolation region is arranged between the non-isolated high-voltage NMOS and the isolated high-voltage NMOS. The high-voltage PMOS, the non-isolated high-voltage NMOS, the isolated high-voltage NMOS and the isolation region are directly arranged in the P-type substrate without an epitaxial layer or a burial layer, thereby reducing manufacture and process cost.

Description

technical field [0001] The present invention relates to semiconductor technology, in particular to a high-voltage complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS for short) integrated structure and a manufacturing method thereof. Background technique [0002] figure 1 It is a structural schematic diagram of a high-voltage CMOS integrated structure in the prior art. like figure 1 As shown, the high-voltage CMOS integrated structure integrates components such as high-voltage PMOS, non-isolated high-voltage NMOS, and isolated high-voltage NMOS. Make the epitaxial layer, and then make high-voltage PMOS, non-isolated high-voltage NMOS, isolated high-voltage NMOS and other components in the superimposed layer structure of the substrate and the epitaxial layer. The specific implementation method is: the first high-voltage NMOS is a non-isolated high-voltage The NMOS and the second high voltage NMOS are isolated high voltage NMOS. Among the...

Claims

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Application Information

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IPC IPC(8): H01L27/088H01L29/06H01L29/78H01L21/336
Inventor 潘光燃文燕王焜石金成高振杰
Owner FOUNDER MICROELECTRONICS INT
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