A method for migrating data from mixed memory in a multi-core processor system

Abstract

The present invention provides a data migration method for a hybrid memory in a multi-core processor system, wherein each processor core has an independent operating voltage and an independent operating frequency and when the operating voltage of one random processor core Px is (reference to the specification) and / or the operating frequency is of the processor core Px is (reference to the specification), data is migrated to a novel memory from a dynamic random access memory. The present invention aims at the data migration method for the hybrid memory in the multi-core processor system, which adopts a DVFS technology; by dynamic voltage and frequency adjustment of different processor cores, migration of the data between a DRAM zone and a NCM zone in the hybrid memory is decided; and not only can power consumption of the memory be effectively reduced, but also overall performance of the system is not affected.

Description

technical field [0001] The invention relates to the field of hybrid memory, in particular to a data migration method for hybrid memory in a multi-core processor system. Background technique [0002] As the feature size becomes smaller and smaller, the power consumption requirements of dynamic random access memory (DRAM) chips are getting higher and higher. Due to the leakage of DRAM storage capacitors, it must be refreshed every once in a while. As the capacity of DRAM is getting larger and larger, Refresh power consumption is also increasing. Especially for servers with large-capacity memory, the proportion of memory power consumption in system power consumption is getting higher and higher. How to reduce memory power consumption is also an urgent problem in the industry. One solution is to limit the self-refresh operation to a certain area of ​​the memory that needs to be saved through the method of partial array self-refresh (PASR) of effective storage space, thereby av...

AI Technical Summary

Problems solved by technology

First of all, if multiple processor cores are not under high load conditions, but after a certain processor core accesses memory, another processor core accesses memory immediately, and after a period of time, another core continues to access memory. As far as the memory is concerned, it is always in a busy state, but for each processor core, it only accesses the memory for a certain period of time. Using the traditional data migration mechanism, data cannot be migrated from DRAM to NCM, thus wasting power consumption

Secondly, when a processor core only interacts with the on-chip cache for a large amount of data within a certain period of time and does not access the mixed memory for a short time, the memory system may mistakenly believe that the processor core is in an idle state. However, if the data in DRAM is migrated to NCM, if the data required by the processor is not cached on-chip at a certain time, then the processor core will frequently access DRAM again. At this time, the data must be migrated from NCM to DRAM again. Guaranteed data access rate requirements

This situation will not only save power consumption, but will generate a large amount of additional power consumption for data migration, and data migration will delay data access and cause system performance degradation

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