Unlock instant, AI-driven research and patent intelligence for your innovation.

Formation method of package structure

An encapsulation structure and plastic encapsulation layer technology, which is applied in the manufacturing of electrical components, electric solid-state devices, semiconductor/solid-state devices, etc., can solve the problems of thinning the thickness and size of the encapsulation structure, and achieve the effect of reducing the size, reducing the difficulty of the process, and being accurate in size.

Active Publication Date: 2018-01-30
NANTONG FUJITSU MICROELECTRONICS
View PDF6 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, the above-mentioned technical means still face various process constraints and cost constraints, and face the problem of further reducing the thickness of the packaging structure

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Formation method of package structure
  • Formation method of package structure
  • Formation method of package structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0035] As mentioned in the background technology, the existing stacked chip packaging technology faces process limitations and cost constraints, which limits the popularization and application of the technology. Moreover, the stacked chip packaging technology is also facing the problem of further reducing the thickness of the packaging structure, in order to further Improve chip integration and reduce size.

[0036] The stacked chip packaging technology can be realized by a through silicon via (TSV for short) technology or a through molding via (TMV for short) technology. However, both the TSV technology and the TSV technology have certain defects.

[0037] Please refer to figure 1 , figure 1It is a schematic cross-sectional structure diagram of introducing a through-silicon via structure in the packaging structure to realize the conduction between chips, including: a carrier 100; a chip 101 fixed on the surface of the carrier 100, and the chip 101 includes an opposite non-f...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A method for forming a packaging structure, comprising: providing a carrier; fixing a chip on a surface of the carrier, the chip has opposite first surfaces and second surfaces, the second surface of the chip includes a functional area, and the first surface of the chip and the carrier surface are fixed to each other The connection key is fixed on the surface of the carrier around the chip, the connection key includes a conductive wire, the connection key includes a first end and a second end exposing the conductive wire, the first end of the connection key is fixed to the carrier surface, and the second end of the connection key The end is higher than or flush with the surface of the functional area of ​​the chip; a plastic sealing layer is formed on the surface of the carrier, the plastic sealing layer surrounds the chip and the connecting key, and the surface of the plastic sealing layer exposes the second end of the connecting key and the surface of the functional area of ​​the chip; on the plastic sealing layer A rewiring layer electrically connected to the second end of the connection key and the functional area of ​​the chip is formed on the surface; a first solder ball is formed on the surface of the rewiring layer; and the carrier is removed afterwards. The forming method of the packaging structure is simple, the process cost is reduced, and the size of the formed packaging structure is accurate and reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a packaging structure. Background technique [0002] In the prior art, the connection between the chip and the external circuit is realized by metal wire bonding (Wire Bonding), that is, wire bonding technology. With the reduction of chip feature size and the improvement of integrated circuit integration, wire bonding technology is no longer applicable to the development needs of technology. [0003] In order to improve the integration level of chip packaging, stacked die package (stacked die package) technology has gradually become the mainstream of technology development. Stacked chip packaging technology, also known as three-dimensional packaging technology, is specifically a packaging technology that stacks at least two chips in the same package. Stacked chip packaging technology can meet the technical requirements of semiconductor d...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/50H01L21/60
CPCH01L21/50H01L24/80H01L24/85H01L2021/60007H01L2224/80H01L2224/85H01L21/60H01L21/568H01L24/19H01L2224/04105H01L2224/12105H01L2224/19H01L2224/20H01L2224/48091H01L2224/48227H01L2224/73265H01L2225/1035H01L2225/1058H01L2924/15311H01L2924/18162H01L2924/00012
Inventor 石磊
Owner NANTONG FUJITSU MICROELECTRONICS