Coreless packaging substrate, pop structure, and methods for fabricating the same

Abstract

A method for fabricating a coreless packaging substrate is provided, which includes: forming a dielectric layer on a conductive plate having a plurality of conductive pads; forming a circuit layer on the dielectric layer and forming in the dielectric layer a plurality of conductive vias that electrically connect the circuit layer and the conductive pads; and removing a portion of the conductive plate so as to cause the remaining portion of the conductive plate to form a plurality of conductive elements, thereby dispensing with a core layer and reducing the material and fabrication cost.

Description

technical field [0001] The present invention relates to a package stack structure, in particular to a package stack structure and its manufacturing method for improving product reliability. Background technique [0002] With the evolution of semiconductor packaging technology, semiconductor devices (Semiconductordevice) have developed different packaging types, and in order to improve electrical functions and save packaging space, multiple packaging structures are stacked to form a package stack structure (Package on Package, POP) , this packaging method can take advantage of the system-in-package (SiP) heterogeneous integration characteristics, and can integrate electronic components with different functions, such as: memory, central processing unit, graphics processor, image application processor, etc., through stack design to achieve system integration Integration, suitable for various thin and light electronic products. [0003] Figure 1A and Figure 1B It is a schema...

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Problems solved by technology

[0006] However, in the existing package stack structure 1, 1', the second package substrate 12 has a core layer 120, resulting in high manufacturing costs and difficult to meet the thinning requirements

[0007] In addition, since the first packaging substrate 11 and the second packaging substrate 12 use solder balls 13 as supporting and electrically connected components, as the number of contacts (i.e. I / O) of electronic products increases, the package If the size of the solder balls 13 remains the same, the distance between the solder balls 13 needs to be reduced, so that bridging (bridge) is prone to occur and short circuits (short) problems occur, thus resulting in low product yield and poor reliability, etc. question

[0008] Moreover, because the volume and height tolerance of the solder ball 13 after reflow is large, that is, the dimensional variation is not easy to control, so that not only the joint is prone to defects (for example, during reflow, the solder ball 13 will first become soft and collapsed. At the same time, after bearing the weight of the second package substrate 12 above, the solder ball 13 is easy to collapse and deform, and then bridges with the adjacent solder ball 13), resulting in poor electrical connection quality, and the grid formed by the solder ball 13 A grid array (grid array) is prone to poor coplanarity, resulting in unbalanced contact stress (stress), which is likely to cause the first and second packaging substrates 11, 12 to be inclinedly connected, and even cause contact offset. question

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