Clock circuit for FPGA verification platform
A technology of clock circuit and verification platform, applied in the direction of electrical components, automatic power control, generation/distribution of signals, etc., can solve the problems of high hardware cost and labor cost, different clock frequency, long development time, etc., to reduce hardware cost and manpower cost, the effect of shortening the development time
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[0020] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0021] The embodiment of the present invention provides a clock circuit for an FPGA verification platform. The FPGA verification platform can verify four different PON systems: XG-PON system, symmetrical 10GEPON system, asymmetrical 10GEPON system and GPON system only through the FPGA chip , the block diagram of the clock circuit is shown in figure 1 shown.
[0022] From the uplink and downlink rates of the four PON systems listed in the background technology, the downlink rates have three different rate levels, namely 9.95328Gbit / s (XG-PON system), 10.3125Gbit / s (symmetrical 10GEPON and asymmetrical 10GEPON systems) ) and 2.48832Gbit / s (GPON system), but there is an obvious multiple relationship between 9.95328Gbit / s and 2.48832Gbit / s, so two different SerDes (SERializer / DESerializer, serializer) in the downlink direction of the PON port ar...
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