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Method and system for generation of downlink scrambling code sequence in WCDMA system

A technology of scrambling code sequence and generating method, which is applied in the field of generation of downlink scrambling code sequence of WCDMA system, can solve the problems of multiple hardware resources, memory consumption, low processing efficiency, etc., so as to improve the scrambling code output efficiency, reduce resource occupation, improve The effect of processing efficiency

Active Publication Date: 2015-12-23
GUANGZHOU HUIRUI SITONG INFORMATION SCI & TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The scrambling code sequence is generated according to a single time slot. If the generated time exceeds the duration of 1 time slot, serious errors will occur in the scrambling of the transmitting end according to the time slot. In addition, if the scrambling code sequence of a single time slot is in Word (each Word32 bit) is also more memory-intensive to store
[0017] The speed of scrambling code generation directly affects the processing efficiency of the downlink channel. Although the existing technology provides several specific methods for scrambling code generation, there are defects in the generation speed, resource occupation, and power consumption.
[0018] The patent "Multi-scrambling code parallel generator and its method in WCDMA cell search" discloses a method for parallel generation of scrambling codes, but each output only generates 8 channels of I / Q data, that is, outputs 8 complex scrambling code sequences , parallel output is not efficient
[0019] "A scrambling code generator for WCDMA system and its implementation method" patent, the scrambling code generation process uses a lot of X / Y status registers, which takes up a lot of hardware resources, and only outputs 3 channels every time the scrambling code is output I / Q data, output 3 complex scrambling code sequences in parallel, low processing efficiency
[0020] "MethodandapparatusforgenerationofdownlinkscramblingcodeinwidebandCDMAmobiledevices" patent, this patent also considers segmented processing to output scrambling code sequences, but the efficiency of parallel output of scrambling codes is low

Method used

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  • Method and system for generation of downlink scrambling code sequence in WCDMA system
  • Method and system for generation of downlink scrambling code sequence in WCDMA system
  • Method and system for generation of downlink scrambling code sequence in WCDMA system

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Embodiment 1

[0049] A method for generating a WCDMA system downlink scrambling sequence, comprising the steps in the following order:

[0050] S1. According to the scrambling code generation device stipulated in the agreement 3GPPTS25.213, such as figure 2As shown, using the device and the initial value of the X / Y sequence specified by the protocol, the state values ​​of the X / Y18-stage shift register can be generated respectively, and the state values ​​are stored in bits and stored in the slow memory. The X / Y state value required for generating complex scrambling code sequence operations per time slot is located in the fast memory, and the real part of the scrambling code sequence is calculated according to the scrambling code number (range 0 to 8191) and the length offset of the complex scrambling code sequence per time slot. The starting position of the state data required by the imaginary part;

[0051] S2. According to the location of the X / Y state sequence storage required to gene...

Embodiment 2

[0058] The invention provides a method for generating downlink scrambling codes in a WCDMA system, which can quickly generate complex scrambling code sequences corresponding to arbitrary downlink scrambling code numbers.

[0059] (1) First, pre-store the status value of the 18th-order X / Y register, and the X / Y status value is currently based on the following figure 2 The shown scrambling code generation circuit produces, combined with the X / Y state register initial phase X (0) = 1, X (1) = X (2) = ... X (16) = X (17) = 0, Y (0 )=Y(1)=…=Y(16)=Y(17)=1, store the value of X\Y state register successively in order, there are 2 in total 18 status. The bit storage is about 8192Word, and the X / Y sequence occupies a total storage space of 16384Word. Considering that it takes up a lot of space, the X / Y status register table is placed in the external slow memory. Calculate the X / Y state value offset according to the downlink scrambling code number and the slot scrambling code length, ...

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Abstract

The invention discloses a method and system for the generation of a downlink scrambling code sequence in a WCDMA (Wide Band Code Division Multiple Access) system, characterized by including the steps of: first, querying the initial position for storing the X / Y sequence state required by generating a corresponding scrambling code sequence through scrambling code offset and data length; second, sectionally abstracting partial data to perform calculation in a fast memory, and generating the X / Y state data required by a current time slot according to time slot data length movement; and finally, successively placing and outputting 32 paths of I / O scrambling code sequences generated by each time slot from a lowest bit to a highest bit by using 32 bits as a unit, wherein 2 bits represent a piece of IQ data, the lowest bit represents an I path, and the highest bit represents a Q path. The method can rapidly generate a corresponding pluralized scrambling code sequence specific to any downlink scrambling code.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a method and system for generating a WCDMA system downlink scrambling code sequence. Background technique [0002] In a WCDMA (WideBandCodeDivisionMultipleAccess, wideband code division multiple access) system, the base station determines the range of the covered cell through the coverage range of the broadcast message. Distinguishing different base stations mainly depends on different downlink scrambling codes, and each cell transmits downlink signals using different scrambling code sequences for scrambling processing. [0003] 3GPPTS25.213 (the3rdGenerationPartnerProjectTechnicalSpecifications25.213) stipulates that the scrambling code sequence is an m-sequence composed of two 18-stage shift registers X / Y, and then a Gold code sequence formed by adding the two m-sequences. The Gold code sequence is a composite code sequence of m sequences, and a new Gold code sequence w...

Claims

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Application Information

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IPC IPC(8): H04J13/10
Inventor 叶恒刘玉珠
Owner GUANGZHOU HUIRUI SITONG INFORMATION SCI & TECH CO LTD
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