Design method aiming at binary program automatic parallelization of multi-core platform

A technology of binary programs and design methods, applied in the direction of program control devices, etc., can solve problems such as inaccessibility and acceleration, and achieve the effect of strong completeness and wide application range

Active Publication Date: 2016-01-13
XI AN JIAOTONG UNIV
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[0009] The purpose of the present invention is to provide a design method for the automatic parallelization of binary programs for multi-core platforms, which can analyze and extract the parallelism in the binary when the sourc

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  • Design method aiming at binary program automatic parallelization of multi-core platform
  • Design method aiming at binary program automatic parallelization of multi-core platform
  • Design method aiming at binary program automatic parallelization of multi-core platform

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[0050] The present invention will be further described in detail below in conjunction with the drawings.

[0051] The invention discloses a method for analyzing and extracting the parallelism in the binary when the source code of the binary program cannot be obtained, and automatically generating the corresponding multi-core parallelized binary program, thereby achieving a method for accelerating the original program using a multi-core platform . The premise of this method is to translate binary into LLVMIR (low-level virtual machine intermediate language), and then first analyze LLVMIR and establish a control flow graph (CFG) to find all loops in the program. The parallelism of static analysis loops fully takes into account the highly optimized algorithms introduced by the compiler when generating the binary. For multi-branch loops, loops that have no direct boundaries in the case of multiple iterations, loops that contain iteration subtypes and scalar dependent loops, and conta...

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Abstract

The present invention discloses a design method aiming at binary program automatic parallelization of a multi-core platform. The method comprises: translating the binary in the multi-core platform into LLVM IR, and then establishing a control flow diagram to find all the cycles in a program by firstly analyzing the LLVM IR; carrying out static analysis on the parallelism of cycles, and removing the cycles difficult in parallel; before regenerating a paralleled code for the cycles, setting simple criteria for the common memory access dependency, adding a corresponding memory address overlapping judging code, thereby reducing the performance loss introduced by the dynamic analysis on the memory access dependency; and then splitting the cycles into two cores to run, and rewriting LLVM IR to generate the paralleled code. According to the method, the parallelism of the binary can be analyzed and extracted under the condition that a binary program source code cannot be obtained, and the corresponding binary program capable of being subjected to multi-core paralleling can be automatically generated, so that the effect of accelerating the original program by using the multi-core platform is achieved.

Description

technical field [0001] The invention belongs to the technical field of binary automatic parallelization, and in particular relates to a design method for automatic parallelization of binary programs aimed at a multi-core platform. Background technique [0002] Since 2004, in order to further improve computing performance and alleviate energy consumption problems, the architecture of microprocessors has tended to be multi-core. In the field of embedded computers, ARM has also launched a series of multi-core microprocessors MPCore in recent years. Although the multi-core transformation of the microprocessor has further improved the performance of the product, the performance potential of the multi-core processor cannot be fully utilized because the traditional upper layer software does not support multi-core parallelization. In addition, due to the wide application of digital image processing technology in recent years, the number of images to be processed has increased and th...

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Application Information

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IPC IPC(8): G06F9/44
Inventor 梅魁志李博良南宝松刘冬冬黄雄刘辉高榕
Owner XI AN JIAOTONG UNIV
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