Digital self-calibration circuit and method of successive approximation analog to digital converter

Abstract

The invention discloses a digital self-calibration circuit of a successive approximation analog-to-digital converter. During analog-to-digital conversion, when carrying out kth bit analog-to-digital conversion, one control code is selected from two selectable control codes according to former bit data at first, and the selected control code is used for controlling a calibration capacitor array and calculating the kth bit data; and before outputting the kth bit data, when carrying out the kth bit analog-to-digital conversion, a logic circuit is controlled to calculate the two selectable control codes corresponding to the (k-1) th bit. The invention further discloses a digital self-calibration method of a successive approximation analog-to-digital converter. The digital self-calibration circuit and method disclosed by the invention can be used for improving the conversion efficiency and the conversion precision, reducing the number of adders and saving the circuit area.

Description

technical field

[0001] The invention relates to the field of semiconductor integrated circuits, in particular to a digital self-calibration circuit of a successive approximation analog-to-digital converter (Successive Approximation Register ADC, SARADC). The invention also relates to a digital self-calibration method of the successive approximation analog-to-digital converter. Background technique

[0002] Successive approximation analog-to-digital converters are widely used in various fields. In the design of the successive approximation analog-to-digital converter, the main errors come from the mismatch of the capacitance and the offset of the comparator. Among them, the capacitance mismatch error introduced during manufacturing has the greatest impact on the performance of the ADC. Traditional solutions such as increasing the capacitor area will seriously increase the design area or reduce the design performance. Therefore, we choose to use on the basis of segment capa...

Examples

Embodiment Construction

[0049] In order to facilitate understanding, a specific successive approximation analog-to-digital converter is taken as an example to illustrate the digital self-calibration circuit of the embodiment of the present invention. The specific successive approximation analog-to-digital converter is as figure 1 The successive approximation analog-to-digital converter includes a first capacitor array 101, a second capacitor array 102, a calibration capacitor array 105, a comparator (COMP) 103, a control logic circuit (SAR&CALLogic) 104 and a memory (CALMemory) 106. A weighted capacitor array is formed by the first capacitor array 102 and the second capacitor array 104 .

[0050] The output terminal PX of the first capacitor array 101 is connected to the first input terminal of the comparator 103 and connected to the common mode level VCM through a switch SP, and the output terminal NX of the second capacitor array 102 is connected to The second input terminal of the comparator 103 ...

technical field

[0001] The invention relates to the field of semiconductor integrated circuits, in particular to a digital self-calibration circuit of a successive approximation analog-to-digital converter (Successive Approximation Register ADC, SARADC). The invention also relates to a digital self-calibration method of the successive approximation analog-to-digital converter. Background technique

[0002] Successive approximation analog-to-digital converters are widely used in various fields. In the design of the successive approximation analog-to-digital converter, the main errors come from the mismatch of the capacitance and the offset of the comparator. Among them, the capacitance mismatch error introduced during manufacturing has the greatest impact on the performance of the ADC. Traditional solutions such as increasing the capacitor area will seriously increase the design area or reduce the design performance. Therefore, we choose to use on the basis of segment capa...

Examples

Embodiment Construction

[0049] In order to facilitate understanding, a specific successive approximation analog-to-digital converter is taken as an example to illustrate the digital self-calibration circuit of the embodiment of the present invention. The specific successive approximation analog-to-digital converter is as figure 1 The successive approximation analog-to-digital converter includes a first capacitor array 101, a second capacitor array 102, a calibration capacitor array 105, a comparator (COMP) 103, a control logic circuit (SAR&CALLogic) 104 and a memory (CALMemory) 106. A weighted capacitor array is formed by the first capacitor array 102 and the second capacitor array 104 .

[0050] The output terminal PX of the first capacitor array 101 is connected to the first input terminal of the comparator 103 and connected to the common mode level VCM through a switch SP, and the output terminal NX of the second capacitor array 102 is connected to The second input terminal of the comparator 103 ...

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