Decryption hardware platform based on FPGA

Abstract

The invention discloses a decryption hardware platform based on an FPGA. The decryption hardware platform is characterized in that the decryption hardware platform comprises a forwarding logic FPGA module, N mutually-independent FPGA decryption sub-modules and an ARM management sub-module which are respectively connected with the forwarding logic FPGA module, and a power supply management module supplying power to the forwarding logic FPGA module, the N mutually-independent FPGA decryption sub-modules and the ARM management sub-module, wherein the N mutually-independent FPGA decryption sub-modules are respectively connected with the ARM management sub-module, and N is no less than 2. The decryption hardware platform provided by the invention meets the decryption requirements of different files and solves the problems that an existing decryption device is single in function and poor in universality. The FPGA has the advantages that the requirements of high-speed data transmission, interfaces and high-frequency data operation are met, high-speed data transmission and high-speed data transportation are realized, and the PFGA is externally provided with a high-speed large-capacity DDR3, so that the storage of rainbow tables is realized.

Description

technical field [0001] The invention relates to the technical field of information security, in particular to an FPGA-based decryption hardware platform. Background technique [0002] In the field of information security, deciphering a large number of encrypted documents is an important content of information services, especially for national defense, public security, and enterprises. Currently, file cracking is generally carried out using a PC, which has poor timeliness and consumes a lot of time. Moreover, there is no general-purpose hardware cracking platform on the market to crack different document file products. [0003] According to the patent search of the existing technology, it is found that Patent No. 201110099441 "ultra-high throughput md5 brute force cracking device based on fpga" provides a design method for brute force cracking MD5 algorithm based on FPGA hardware. The defect of this patent lies in: brute force cracking consumes , the cracking performance is...

AI Technical Summary

Problems solved by technology

Currently, file cracking is generally carried out using a PC, and the timeliness of cracking is poor, and cracking takes a lot of time

Moreover, there is no general-purpose hardware cracking platform on the market to crack different document file products.

[0003] According to the patent search of the existing technology, it is found that Patent No. 201110099441 "ultra-high throughput md5 brute force cracking device based on fpga" provides a design method for brute force cracking MD5 algorithm based on FPGA hardware. The defect of this patent lies in: brute force cracking consumes , the cracking performance is not as good as the rainbow table technology cracking

Moreover, the clock of the MD5 core computing module of the patent is only 50MHz, and the clock frequency is too low

[0004] Patent No. 200510025068 "File password cracking method" proposes a PC-based exhaustive cracking solution, which does not involve cracking the rainbow table, and the cracking of design defects is too time-consuming

[0005] Patent No. 201310326225 "Recovery Method and Device for Hash Value Password" proposes a cracking scheme based on PC-based rainbow table. The design defect of this patent is that the PC needs to generate a rainbow table, and then crack it after the generation of the rainbow table is completed. The duration increases the time to generate the rainbow table, which obviously takes too long

[0007] EfficientImplementationofHashAlgorithmonaProcessor proposes a solution based on the ARM processor to implement the MD5 algorithm. The disadvantages are: the speed and efficiency of the ARM processor are not as good as FPGA, and the solution does not involve the cracking of the rainbow table, the cracking function is single, and the general performance of the hardware platform is poor.

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