Array substrate and manufacturing method thereof, display panel and display device

Abstract

The invention provides an array substrate, a fabrication method of the array substrate, a display panel and a display device. The fabrication method of the array substrate includes the steps of forming graphs of a grid, a grid insulation layer, an active layer and a source and drain layer; forming a transparent electrode layer on the surface of the source and drain layer; forming graphs of a source and a drain according to the source and drain layer through an etching process, and forming a graph of a pixel electrode according to the transparent electrode layer; enabling the pixel electrode to be in direct contact with the drain. According to the fabrication method of the array substrate, the pixel electrode is in direct lap joint with the drain of a TFT structure, via holes are not needed to be formed in the insulation layer, and thus on the one hand, one etching process is omitted, material cost is lowered, and production efficiency is improved; on the other hand, the product yield can be improved. Besides, the flatness of the graphs on the surface of the array substrate can be improved, the probability of misalignment in the subsequent alignment film preparation process is reduced, and the display effect is improved finally.

Description

technical field [0001] The present invention relates to the field of display technology, in particular, to an array substrate and a preparation method thereof, a display panel and a display device. Background technique [0002] The display panel of TFT-LCD includes an array substrate and a color filter substrate. The array substrate is generally prepared with thin film transistors, pixel electrodes, and signal lines such as gate lines and data lines; The electrode lines are prepared on the array substrate. [0003] A thin film transistor includes a gate, a gate insulating layer, an active layer, a source and a drain. When preparing thin-film transistors on an array substrate, generally, the above-mentioned patterns are sequentially formed in the order of gate→gate insulating layer→active layer→source and drain; after the patterns of the source and drain are prepared , usually continue to form a layer of insulating passivation layer (PVX layer), and form a via hole through ...

AI Technical Summary

Problems solved by technology

[0004] In the above-mentioned existing process of preparing the array substrate, it is necessary to form a via hole through the PVX layer to connect the pixel electrode to the drain electrode, which requires an additional process for forming a via hole, resulting in an increase in material consumption, and The extension of process time will lead to higher cost and lower production efficiency

At the same time, the pixel electrode is connected to the drain through the via hole, which requires higher process requirements for preparing the pixel electrode, resulting in a decrease in product yield.

In addition, the via holes will also increase the level difference on the array substrate and reduce the flatness of each pattern on the array substrate, which will lead to poor orientation during the process of forming the alignment film, and ultimately affect the display effect of the TFT-LCD.

Images