Method for forming gate oxide layers with different thicknesses in gate last process

Abstract

The invention provides a method for forming gate oxide having different thickness in the gate-last process. The method comprises the following steps: providing a semiconductor substrate which comprises a core device region and an IO device region, the semiconductor substrate at the core device region and the IO device region is covered with an oxide layer; forming a dielectric layer covering the semiconductor substrate and the oxide layer, wherein the dielectric layer has gate openings in the core device region and the IO device region respectively; forming a high-K material layer and a capping layer in sequence, wherein the high-K material layer covers the surface of the dielectric layer, and the bottom portions and the side walls of the gate openings, and the capping layer covers the high-K material layer; injecting an oxygen cleanser to the core device region; and carrying out annealing on the semiconductor substrate to enable the oxygen cleanser to remove at least a part of oxygen in the core device region. The gate oxide of the core device region does not need to be removed, so that the problems of dielectric layer loss, IO device gate oxide loss and non-uniformity and the like can be prevented.

Description

technical field [0001] The invention relates to a gate-last process, in particular to a method for forming gate oxide layers with different thicknesses in the gate-last process. Background technique [0002] With the development of semiconductor technology, the critical dimension (CD, Critical Dimension) is continuously reduced, and the precise control of the thickness of the gate oxide layer becomes more important than in the past. [0003] In the gate-last process (HKMG last technology) of high-K dielectric layer plus metal gate, because in multiple thermal process steps, such as source-drain injection activation annealing, the thickness of the gate oxide layer becomes thicker, so the dummy gate After the dummygate is removed, the gate oxide is removed and grown again. The smaller the thickness of the gate oxide, the greater the proportional increase in thickness during the thermal processing steps. [0004] In the prior art, a core device (core device) and an IO device ...

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Problems solved by technology

[0014] still refer to Figure 5 , in the process of removing the IO gate oxide layer 11 in the core device area, if the photoresist is not used to protect the IO device area, it will cause the loss of the dielectric layer 13, the loss of the IO gate oxide layer 11 in the IO device area, etc. ; If a photoresist is used to protect the IO device region, it will cause exposure and removal of the photoresist at the gate opening 131 of the IO device region

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