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VDMOS trench etching method and VDMOS

A trench and etching process technology, used in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of trenches that do not meet the requirements and the etching process is over-etched, so as to reduce the chemical reaction rate and avoid over-etching. Controllable effect of etching and etching process

Inactive Publication Date: 2016-04-13
PEKING UNIV FOUNDER GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In the process of realizing the present invention, the etching process in the prior art easily leads to over-etching, resulting in the grooves obtained by etching not meeting the requirements

Method used

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  • VDMOS trench etching method and VDMOS
  • VDMOS trench etching method and VDMOS
  • VDMOS trench etching method and VDMOS

Examples

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Embodiment Construction

[0025] The specific implementation manners of the present invention will be further described below in conjunction with the drawings and examples. The following examples are only used to illustrate the technical solution of the present invention more clearly, but not to limit the protection scope of the present invention.

[0026] The invention provides a vertical double diffused metal-oxide semiconductor field effect transistor VDMOS trench etching method, the method adopts an inductively coupled plasma etching process to etch a semiconductor substrate in a vacuum cavity, such as image 3 As shown, the method includes:

[0027] Step 301, providing a vacuum cavity and a semiconductor substrate;

[0028] Step 302, etching the semiconductor substrate in the vacuum chamber; wherein, during the etching process, the pressure of the vacuum chamber is 120 to 130 mTorr.

[0029] Compared with the trench etching process in the prior art, the VDMOS trench etching method provided by th...

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Abstract

The invention provides a VDMOS trench etching method. According to the method, a semiconductor substrate is etched in a vacuum cavity by adoption of an inductive coupling plasma etching technology, and in the etching process, the pressure of the vacuum cavity is 120 to 130 millitorrs. In the method, since the pressure in the vacuum cavity in the etching process is improved, existence time of plasma in the bottom of a trench can be effectively reduced, thereby reducing the chemical reaction rate, enabling the etching process to be relatively controllable, and effectively avoiding over-etching of the bottom of the trench.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a VDMOS trench etching method and VDMOS. Background technique [0002] For trench VDMOS, trench etching is a very important step. The morphology of the trench (steepness of the side wall / topography of the bottom of the trench, etc.) ) / IGSS (gate-source leakage) / Vth (turn-on voltage), etc. have a great influence. [0003] Generally, in the prior art, the ICP (Inductively Coupled Plasma Etching) process is used for trench etching, that is, the processed silicon wafer is etched using a radio frequency electrode in a vacuum chamber. figure 1 The etching process of this etching process is shown. The process is a simultaneous chemical reaction and physical bombardment. After the plasma gas is passed into the vacuum chamber, it is accelerated in the power plant formed by the upper and lower electrodes to bombard the silicon wafer. The etching process is divided into two steps...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/3065
Inventor 赵圣哲
Owner PEKING UNIV FOUNDER GRP CO LTD