A set-resistant hardened ring oscillator

Abstract

The invention discloses an anti-SET solidified ring oscillator comprising N stages of master ring oscillators and N output voters. The N stages of master ring oscillators comprise N stages of time-delay units. Each stage of time-delay unit outputs three pairs of differential outputs and the N stages of time-delay units output 3N pairs of differential outputs in total. Each output voter is connected with a stage of time-delay unit in the N stages of master ring oscillators and receives the three pairs of differential outputs of the stage of time-delay unit as inputs, and outputs an effective value after performing a majority voting on the inputs. The N is an integer greater than 1. The anti-SET solidified ring oscillator is well immune to the SET, may generate uniform multi-phase outputs, prevents a redundant loop phase synchronization problem due to VCO solidification in the prior art, does not add extra time delay in the loop, and has few influences on the loop oscillation frequency.

Description

technical field [0001] The invention relates to the technical field of oscillators, in particular to a single-event transient (Single-Event Transient, SET) reinforced ring oscillator. Background technique [0002] In the radiation environment, after the high-energy particles bombard the sensitive nodes of the circuit, the "electron-hole" pairs produced by the impact ionization are transmitted and collected under the action of the electric field and concentration gradient of the transistor, so that the output voltage or current fluctuates, resulting in The circuit produces erroneous outputs, creating a SET effect. Integrated circuits are susceptible to various failures caused by SET. [0003] Ring oscillators are mainly used in circuits such as clock generation, frequency multiplication and frequency synthesis. The ring oscillator is a typical feedback system, which works in a periodic oscillation state. An error generated by a sensitive node will be transmitted to the enti...

AI Technical Summary

Problems solved by technology

The common terminal of the three VCO loops is only the control voltage Vcont, which can only ensure that the oscillation frequency of the three VCO loops is the same, but cannot control the loop phase, so the clock phases generated by the three loops are random, resulting in the voting circuit Unable to output correct clock

However, the voting structure introduced by it destroys the consistency of the structure of each level of the loop, which will cause the phase difference of the output of the VCO at all levels to be uneven, and it is difficult to apply in the occasion where multi-phase output is required. In addition, the voting structure introduced increases the loop Delay, will reduce the operating frequency of the VCO

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