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An asic design clock network extraction system

A clock network and extraction system technology, which is applied in computing, instruments, electrical digital data processing, etc., to reduce error rates and improve work efficiency

Active Publication Date: 2019-03-19
SHANDONG HAILIANG INFORMATION TECH RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The present invention provides a system for analyzing and extracting the clock network in the ASIC design front-end netlist aiming at the current needs and the shortcomings of the development of the prior art

Method used

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  • An asic design clock network extraction system
  • An asic design clock network extraction system
  • An asic design clock network extraction system

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Embodiment

[0017] attached figure 1 A schematic structural representation of the ASIC design clock network extraction system described in this embodiment; as attached figure 1 As shown, the central box area in the figure is the system of the present invention, the left side of the system is the input file, and the right side is the output file. It can be seen from the figure that the system consists of three parts: clock mode analysis unit, clock domain analysis unit, and original clock network output unit. The input files on the left include ASIC front-end netlist and mode constraint files; the output files on the right include original clock files and reconstruction template files.

[0018] The ASIC design clock network extraction system described in this embodiment, the clock mode analysis unit generates various parameters of the ASIC design for clock network analysis in different operating modes according to the input mode constraint file, and transmits them to the clock domain anal...

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Abstract

The invention discloses an ASIC design clock network extraction system, which relates to the field of chip design. The system is based on an EDA tool and uses an analysis algorithm implemented by a TCL script to complete the analysis and extraction tasks of a large-scale complex clock network in ASIC design; the system consists of three parts Composition: clock mode analysis unit, clock domain analysis unit, original clock network output unit. By applying the present invention, the analysis and extraction of the ASIC design clock network can be completed highly automatically, which can greatly reduce the error rate caused by the traditional manual analysis method, and can also greatly improve work efficiency.

Description

technical field [0001] The invention relates to the field of chip design, in particular to an ASIC design clock network extraction system. Background technique [0002] Usually in the early stage of ASIC back-end design, multi-faceted analysis of the front-end netlist is required. In particular, a detailed and accurate understanding of the clock network structure is a prerequisite for ensuring the performance and quality of the chip's back-end design. In the ASIC back-end design process, whether it is system testability design or automatic layout and routing, it is necessary to carefully analyze and construct the original clock network architecture. Especially in the face of the situation of many functional modes and complex clock structures in today's VLSI, how to accurately and efficiently complete the analysis and extraction of the clock network from the ASIC front-end design netlist is an important link. [0003] Conventional ASIC design clock network analysis and extr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
CPCG06F30/398
Inventor 唐涛石广刘海林王硕
Owner SHANDONG HAILIANG INFORMATION TECH RES INST
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