Method for Improving Performance Fluctuation of Semiconductor Devices

Abstract

The invention provides a method for improving semiconductor device performance fluctuation. The method comprises the steps that a production and manufacturing performing system dispatches the batch of wafers to corresponding machines according to the technological process to which the wafer batches belong and performs specified technological programs; the lightly-doped drain ion injection part in the production technological process is optimized into the automatic compensation technological integration process, and etched gate electrode key dimensions are grouped; a gate electrode etching program name list is established for the production technology including the automatic compensation technological integration process; dispatching of the gate electrode etching step is performed according to the production and manufacturing performing system; intervention of control programs is performed before the batch of wafers are automatically selected to enter a reaction chamber by the system of an etching machine so that all the wafers of the same batch enter the same etching reaction chamber; and the production and manufacturing performing system performs the automatic compensation technological integration process in the lightly-doped drain ion injection step, and lightly-doped drain ion injection is performed according to the technological programs corresponding to the groups of the gate electrode key dimensions.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, and more specifically, the invention relates to a method for improving performance fluctuation of semiconductor devices. Background technique [0002] As the minimum critical dimension of the gate of the short trench device becomes smaller and smaller, it is more difficult to control the fluctuation of its performance. Theoretically, the shallow doped drain / pocket implant can be fine-tuned for the variation of gate critical dimension to control the variation of device performance (positive feedback). However, this method is difficult to implement in the actual production of a semiconductor production line and its manufacturing execution system that dispatch workers in units of wafer batches. The reasons are as follows: [0003] Firstly, the gate etching machine has multiple etching reaction chambers (for example, 3), and there are non-negligible deviations among them. It is dangerous...

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Problems solved by technology

It is dangerous to do shallow doped drain / annular implant forward feedback based on the gate critical dimension average of different etch chambers

[0004] Secondly, since the production system of the 8-inch factory is based on batches (lots) rather than wafers (wafers) as in the 12-inch length, the wafers that have run different etching reaction chambers in the same batch are grouped, and the key Ion implantation with corresponding dimensions is less operable in actual production

[0005] Again, if the gate etching is performed in a single reaction chamber, although the above problems can be solved, it will be at a huge cost of loss of production capacity

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