Systolic structure matrix multiplier based on FPGA (Field Programmable Gate Array) and implementation method thereof

Abstract

The invention provides a systolic structure matrix multiplier based on an FPGA (Field Programmable Gate Array) and an implementation method thereof. The systolic structure matrix multiplier comprises a multiplier array composed of M x R node units, a clock control module, a data input control module and a data output control module; the M x R node units are interconnected by a two-dimensional mesh array structure of M rows and R columns, used for performing a multiply-accumulate calculation on data, and have systolic structures in each data direction of rows and columns; the clock control module is used for providing a clock, controlling the whole calculation process, and recoding the state of a current multiplier; the data input control module is used for controlling an input matrix to input by rows or by columns, and making the input matrix to satisfy an input rule of time alignment; and the data output control module is used for outputting the calculation results by rows or by columns under the control of an output clock. The implementation method of the matrix multiplier provided by the invention can enable data to enter the matrix multiplier according to the input rule of the systolic structure by rows or by columns, and perform a multiply-add operation and output the calculation results. The systolic structure matrix multiplier based on the FPGA provided by the invention has the advantages of being very high in calculation performance, good in modularity and convenient in reconfiguration.

Description

technical field [0001] The invention relates to the field of FPGA technology and high-performance computing technology, in particular to an FPGA-based systolic matrix multiplier and an implementation method thereof. Background technique [0002] Matrix multiplication is widely used as a basic operation in scientific computing, digital signal processing, etc., and its computing performance directly affects the overall performance of the system. Gradually become the bottleneck of system computing performance. [0003] Previous matrix multiplication operations usually use hardware as a general-purpose processor and software to implement matrix multiplication, or use hardware as a dedicated digital signal processor (Digital Signal Process, DSP) to achieve. This type of processing method is relatively mature in technology, complete in implementation tools, and simple in programming. However, due to its internal structure and platform limitations, it is not suitable for occasions...

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Problems solved by technology

[0007] Aiming at the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a method that can solve the problem that the fan-out of the input module of the existing matrix multiplier is too high, it is difficult to achieve hig

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