Memory system and programming, erasing and reading method

Abstract

The invention discloses a memory system, a programming method, an erasing method and a reading method. The memory system comprises first memory units, P first word lines, Q first bit lines, Q second bit lines and R first source lines, wherein the first memory units are arranged in a manner of P rows and Q columns; P is not smaller than 1, Q is not smaller than 1 and R is not smaller than 1; the first memory unit positioned in the column q and row p is connected with the q-th first bit line, p is not smaller than 1 and is not greater than P, and q is not smaller than 1 and is not greater than Q; the first memory unit positioned in the column q and row p+1 is connected with the q-th second bit line; the first memory units in the row P are connected with the P first word lines in a one-to-one corresponding manner; the s-th first word line is connected with the (s+1)-th first word line, and s is an odd number which is not smaller than 1 and is smaller than P; when P is an even number, R=P / 2, the first memory units positioned in the row a and the row a-1 are all connected with the (a / 2)-th first source line, and a is an even number which is not smaller than 2 and is not greater than P; when P is an odd number, R=(P+1) / 2, the first memory units positioned in the row b and the row b-1 are all connected with the (b / 2)-th first source line, b is an even number which is not smaller than 2 and is smaller than P, and the first memory units positioned in the row P are all connected with the R-th first source line.

Description

Technical field [0001] The present invention relates to the field of memory, in particular to a memory system and programming, erasing and reading methods. Background technique [0002] Existing chips often need to integrate two types of memory, one type is large capacity and low performance, used to store data that does not need to be frequently erased; the other type is small capacity and high performance, used to store data that requires frequent erase and write. [0003] High-performance memories often require a larger area of ​​active area. In order to be compatible with small-capacity and high-performance memories on a chip, large-capacity and low-performance memories are often larger in area, which leads to a larger area of ​​the entire chip. increase. [0004] Another approach is to use different processes to prepare these two types of memories and then integrate them. However, this approach obviously requires a lot of time and energy consumption. Summary of the invention ...

AI Technical Summary

Problems solved by technology

However, this approach obviously takes a lot of time and energy

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