Memory system and programming, erasing and reading method

A storage system and memory technology, applied in the field of memory, can solve the problems of multiple time, energy consumption, and consumption, and achieve the effect of reducing the chip area

Active Publication Date: 2019-10-22
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this approach obviously takes a lot of time and energy

Method used

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  • Memory system and programming, erasing and reading method
  • Memory system and programming, erasing and reading method
  • Memory system and programming, erasing and reading method

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Embodiment Construction

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] Such as figure 1 As shown, the first memory provided by the embodiment of the present invention includes: first memory cells arranged in P rows and Q columns, and P first word lines WL 1 (0, P-1), Q first bit lines BL 1 (0, Q-1), Q second bit lines BLPD (0, Q-1), and R first source lines SL 1 (0, R-1), P≥1, Q≥1, R≥1.

[0035] The first memory cell located in the p-th row and the q-th column is connected to the q-th first bit line BL 1 , P≥p≥1, Q≥q≥1, and the first memory cell located in the p+1th row and the qth column is connected to the qth second bit line BLPD.

[0036] The P rows of first memory cells and the P first word lines WL 1 One-to-one correspondence connection, the sth first word line and the s+1th first...

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Abstract

The invention discloses a memory system, a programming method, an erasing method and a reading method. The memory system comprises first memory units, P first word lines, Q first bit lines, Q second bit lines and R first source lines, wherein the first memory units are arranged in a manner of P rows and Q columns; P is not smaller than 1, Q is not smaller than 1 and R is not smaller than 1; the first memory unit positioned in the column q and row p is connected with the q-th first bit line, p is not smaller than 1 and is not greater than P, and q is not smaller than 1 and is not greater than Q; the first memory unit positioned in the column q and row p+1 is connected with the q-th second bit line; the first memory units in the row P are connected with the P first word lines in a one-to-one corresponding manner; the s-th first word line is connected with the (s+1)-th first word line, and s is an odd number which is not smaller than 1 and is smaller than P; when P is an even number, R=P / 2, the first memory units positioned in the row a and the row a-1 are all connected with the (a / 2)-th first source line, and a is an even number which is not smaller than 2 and is not greater than P; when P is an odd number, R=(P+1) / 2, the first memory units positioned in the row b and the row b-1 are all connected with the (b / 2)-th first source line, b is an even number which is not smaller than 2 and is smaller than P, and the first memory units positioned in the row P are all connected with the R-th first source line.

Description

Technical field [0001] The present invention relates to the field of memory, in particular to a memory system and programming, erasing and reading methods. Background technique [0002] Existing chips often need to integrate two types of memory, one type is large capacity and low performance, used to store data that does not need to be frequently erased; the other type is small capacity and high performance, used to store data that requires frequent erase and write. [0003] High-performance memories often require a larger area of ​​active area. In order to be compatible with small-capacity and high-performance memories on a chip, large-capacity and low-performance memories are often larger in area, which leads to a larger area of ​​the entire chip. increase. [0004] Another approach is to use different processes to prepare these two types of memories and then integrate them. However, this approach obviously requires a lot of time and energy consumption. Summary of the invention ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/10G11C16/14G11C16/26
Inventor 杨光军
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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