Unlock instant, AI-driven research and patent intelligence for your innovation.

A method for checking the connection relationship of integrated circuit line network

A technology of connectivity and integrated circuits, applied in electrical digital data processing, instruments, computing, etc., can solve the problems of high memory usage, long running time, slow running speed, etc.

Active Publication Date: 2019-05-28
北京华大九天科技股份有限公司
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Aiming at the problems of slow running speed, long running time and large memory occupation faced by very large scale integrated circuit layout verification tools, especially ERC and LVS tools, the present invention proposes an efficient and simple concurrent connection relationship checking method

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A method for checking the connection relationship of integrated circuit line network
  • A method for checking the connection relationship of integrated circuit line network
  • A method for checking the connection relationship of integrated circuit line network

Examples

Experimental program
Comparison scheme
Effect test

specific Embodiment approach 1

[0041] image 3 is a schematic diagram of an inverter circuit, identifying nets that cannot be connected to the power supply VDD.

[0042] The inverter has a total of four nets, and each net has a number (ID) and a name: 1=VDD, 2=IN, 3=OUT, 4=GND. There are two devices: the G, S, and D terminals of the device M1 are respectively connected to the wire nets IN, VDD, and OUT; the G, S, and D terminals of the device M2 are respectively connected to the wire nets IN, OUT, and GND.

[0043] Using forest representation, the recognition process is completed in four steps:

[0044] (1) Initialize the connectivity table

[0045] Since there are 4 nets in total, the initial connectivity table contains 4 nodes, such as Figure 4 (left). Each node has a pointer to itself (the pointer to the node itself is not drawn). The node number in the figure represents the network ID.

[0046] (2) Read the device database and merge the connected relationship formed by the device into the connect...

specific Embodiment approach 2

[0053] The example of the first specific implementation mode is still used, but a connected relationship table represented by an array is used. The identification process is as follows:

[0054] (1) Initialize the connectivity table

[0055] The size of the initialized array is 5, and the values ​​of all elements are the same as their subscripts, and the elements with a subscript of 0 are not used, such as Figure 5 (upper left).

[0056] (2) Read the device database and merge the connected relationship formed by the device into the connected relationship table

[0057] Assume that the device read out first is M2, and M2 connects nets 3 and 4. Access the element with subscript 3 in the array, read the value of this element as a new subscript to access its parent element, and so on, until the element with the same subscript and value (root element) is reached. The root element of 3 in this embodiment is 3 itself. Also find the root element of 4, which is still 4. Change t...

specific Embodiment approach 3

[0063] The connection diagram of the line network is: VDD-N 1 -VSS-N 2 -N 3 , to identify "network connected to VSS, but not connected to VDD", the connection path is not allowed to cross VDD or VSS, and VDD and VSS itself are not output.

[0064] If the method of Embodiment 1 or Embodiment 2 is adopted directly, all the nets are connected, and there is no required net. However, according to the actual circuit design requirements, VDD or VSS can only appear at both ends of the current path, not in the middle, so there is a VDD-N 1 -VSS and VSS-N 2 -N 3 Two pathways, not one. Find the line network connected to VSS (excluding VDD and VSS itself) from these two paths. 1 , N 2 and N 3 , the net connected to VDD is N 1 . N 2 and N 3 That's what you want.

[0065] Two net connection relationship tables are used, the first table records the connection relationship between each net and VDD, and the second table records the connection relationship between each net and VSS....

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a method for detecting connection relations of integrated circuit line nets, and belongs to the technical field of EDA (electrical design automation), especially the ERC (electric rule check) and LVS (uniformity comparison of an integrated circuit layout and a schematic) in the layout verification field. With respect to the integrated circuit layout composed of N line nets and D instruments, the connection relations are recorded only by a connection relation table with magnitude of N; the time and space complexities are clearly superior to a method based on a bipartite graph; the connection relation detection method provided by the invention has the advantages of occupying little memory, rapid operation speed and easy realization; the operation efficiency of related EDA software is improved; and the design cycle of the integrated circuit is shortened.

Description

technical field [0001] The technical field is EDA (Electrical Design Automation), especially ERC (Electrical Rule Check) and LVS (Consistency Check between Integrated Circuit Layout and Schematic Diagram) in the field of layout verification. Background technique [0002] In recent years, integrated circuit technology has been developing in accordance with "Moore's Law". The feature size of the chip is getting smaller and smaller, the integration of a single chip is getting higher and higher, and the manufacturing process is getting more and more complicated. With the expansion of chip scale and the improvement of manufacturing technology, the verification required in each stage of integrated circuit design is also increasing. Usually, integrated circuit design is divided into two stages: front-end and back-end. The front-end is mainly for logical design, and the back-end is mainly for physical design. The layout of the back-end design must be consistent with the principle ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 王国庆丁丰庆毛凌颖李志梁刘晓明陈光前杨晓东
Owner 北京华大九天科技股份有限公司