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Method and device for designing layout

A design method and layout technology, applied in the direction of design optimization/simulation, calculation, special data processing applications, etc., can solve problems such as heavy workload and long development cycle, to solve the problem of heavy workload, long development cycle, and improve work efficiency effect

Inactive Publication Date: 2016-06-08
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] The main purpose of the present invention is to provide a layout design method and device to at least solve the problems of heavy workload and long development cycle in the process design process of the above-mentioned related LDE

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  • Method and device for designing layout
  • Method and device for designing layout
  • Method and device for designing layout

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Embodiment 1

[0048] Due to the significant LDE in the advanced technology, it is bound to cause the layout simulation results to a certain extent to depend on the layout of the layout, so the simulation results of the schematic diagram and the layout simulation results are quite different, making it difficult to grasp the design margin of the schematic diagram, which eventually leads to The interactive workload between schematic diagram and layout is greatly increased, which prolongs the development cycle. Based on this, this embodiment provides a design method for the layout layout of advanced technology with significant LDE effect. A transition step is introduced between the schematic simulation and layout simulation of the traditional design process, which can be more accurate before the layout is completed. The predicted layout simulation results have changed the situation that the simulation results can only be obtained after the layout design is completed. Moreover, to a large extent...

Embodiment 2

[0054] This embodiment provides a design process for advanced technology including layout-dependent effects (LDE, Layout-Dependent Effects), including:

[0055] Step 1, the design of the model and schematic diagram of LDE;

[0056] Step 2, the construction of the simulation circuit;

[0057] Step 3, carry out simulation;

[0058] Step 4, for analog circuit design, it is necessary to set layout parameters for key devices (generate MOD_LDE_PRESET), and perform simulation; for digital circuit design, ignore this step;

[0059] Step 5, generate the layout, layout adjustment and simulation through the design tool;

[0060] Step 6, wiring, physical verification, parameter extraction and layout simulation.

[0061] In the implementation process, the simulation operation in steps 3-6 can jump back to step 1 for schematic design, the layout simulation and physical verification operation in step 6 can jump back to wiring operation, step 5 simulation operation and step 6 After the wi...

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Abstract

The invention discloses a method and a device for designing layout. The method comprises: according to a schematic diagram of a completed electronic circuit, determining layout parameters of key components; according to the layout parameters of the key components, simulating the electronic circuit; and according to a simulation result, adjusting the schematic diagram of the electronic circuit. The method and the device solve technical problems that workload in a LDE process design flow is large and development cycle is long.

Description

technical field [0001] The invention relates to the field of electronic circuits, in particular to a layout design method and device. Background technique [0002] With the continuous shrinking of the process size, the impact of the layout-dependent effects (Layout-Dependent Effects, LDE) in the standard complementary metal-oxide-semiconductor (CMOS) process becomes more and more prominent. In 40nm / In the process of 45nm and below, LDE can no longer be ignored. Therefore, the model of the advanced process has introduced parameters related to LDE on the basis of the traditional model. However, a large part of these parameters can only be valid after the layout is completed, and then applied in the layout simulation (Post-LayoutSimulation). If the traditional design process is adopted, that is, the schematic design is first completed, and then the layout, wiring, and simulation are performed, which will inevitably cause a lot of rework and greatly increase the workload of th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/392G06F30/394G06F30/20G06F30/398
Inventor 朱光陈先敏冯光涛杨家奇
Owner SEMICON MFG INT (SHANGHAI) CORP
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