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A clock circuit for i/q demodulation in a soc chip

A technology of clock circuit and clock generation circuit, applied in demodulation, electrical components, modulation transfer, etc., can solve the problems of signal attenuation, limited bandwidth, inconvenient correction, etc., achieve no bandwidth limitation, reduce power consumption, reduce Realize the effect of cost

Inactive Publication Date: 2018-08-17
GUANGZHOU SYSUR MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The multi-phase structure RC filter mainly uses resistance and capacitance to cross-connect to form a ring. This structure is limited by bandwidth and the signal will be attenuated.
At the same time, the specific number of capacitors and resistors required needs to be determined according to the operating frequency, which is not easy to correct

Method used

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  • A clock circuit for i/q demodulation in a soc chip
  • A clock circuit for i/q demodulation in a soc chip
  • A clock circuit for i/q demodulation in a soc chip

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Embodiment Construction

[0026] The specific embodiment of the present invention will be further described below in conjunction with accompanying drawing:

[0027] refer to figure 1 , an I / Q demodulation clock circuit in a SoC chip, including an I clock generation circuit, a delay module, a counter and a control circuit module, the delay module includes multiple groups of delay branches, and the delay branch The circuit includes a branch switch and a delay unit, the output end of the I clock generation circuit is connected to the delay unit through a branch switch, and the delay units in the multiple groups of delay branches are connected in series successively, and the multiple groups The output end of the delay unit of the last group of delay branches in the delay branch is connected to the input end of the counter and the control circuit module, and the output ends of the counter and the control circuit module are respectively connected to the branches of multiple groups of delay branches. Road sw...

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Abstract

The invention discloses an I / Q demodulation clock circuit in an SoC chip. The I / Q demodulation clock circuit comprises an I clock generating circuit, a delay module and a counter and control circuit module; the delay module comprises multiple branch switches and delay units, the output end of the I clock generating circuit is connected to the delay units through the branch switches, the multiple delay units are sequentially connected in series and output to the input end of the counter and control circuit module, and the output end of the counter and control circuit module is connected with control ends of the multiple branch switches. Circuit operation power consumption is reduced by adopting the branch switches, and the delay module is used for adjusting the phase, so that it is unnecessary to improve the work frequency or additionally arrange a phase correction module, bandwidth limitation is avoided, the circuit is simple in structure and can be simplified and optimized through the method of module reuse, redundancy part clipping and the like, and the cost of chip obtaining is reduced. The I / Q demodulation clock circuit and method in the SoC chip can be widely applied to electronic circuit field.

Description

technical field [0001] The invention relates to the field of electronic circuits, in particular to an I / Q demodulation clock circuit in an SoC chip. Background technique [0002] SoC is an acronym for System on Chip, that is, a system on a chip. As the name implies, it is to integrate key parts of the system, such as microprocessors, analog IP cores, digital IP cores, and memory, into a single chip. Many integrated circuits with specific functions are assembled on one chip, which makes the SoC chip have the advantages of small size, light weight, multi-function, high speed and low cost, and is widely used in communication, transportation, logistics and other fields. [0003] The Barkhausen criterion is the basic condition to ensure loop oscillation, and the loop gain of the negative feedback circuit must meet the following conditions: [0004] [0005] When the loop gain of the negative feedback circuit satisfies the above conditions, the loop can oscillate, otherwise, ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/04H03D7/16
CPCG06F1/04H03D7/165
Inventor 胡建国段志奎林格李启文王德明
Owner GUANGZHOU SYSUR MICROELECTRONICS