ESD (electrostatic discharge) power supply clamping protection circuit

Abstract

The invention provides an ESD (electrostatic discharge) power supply clamping protection circuit. The ESD power supply clamping protection circuit comprises a power supply end, a grounding end, an electrostatic discharge (ESD) detection circuit, a triggering holding circuit and a leakage circuit, wherein the power supply end is used for supplying a power supply voltage; the grounding end is used for supplying a ground electrical level; the ESD detection circuit is used for detecting an ESD shock signal and outputting an ESD trigger signal; the triggering holding circuit is used for triggering a discharging transistor in the leakage circuit to be switched on according to the ESD trigger signal, and prolonging the starting time of the discharging transistor through a feedback mechanism; and the leakage circuit is used for supplying a low-resistance channel between the power supply and the ground when the ESD trigger signal output by the triggering holding circuit is received so as to realize electrostatic current discharge. The ESD power supply clamping protection circuit provided by the invention can effectively restrain current leakage of the electrostatic protection circuit and can effectively prevent the internal circuit from being damaged by electrostatic discharge.

Description

technical field [0001] Embodiments of the present invention relate to the technical field of electrostatic discharge test simulation, and in particular to an ESD power supply clamp protection circuit. Background technique [0002] Electrostatic Discharge (ESD for short) refers to the process of charge transfer caused by close or direct contact between objects with different electrostatic potentials. With the rapid development of semiconductor technology, the feature size of devices in integrated circuits has been continuously reduced, reaching the nanometer level. However, with the shrinking of the transistor feature size, the gate oxide layer of the device is getting thinner and thinner (under the standard 65nm bulk silicon process, the gate oxide thickness is about 2nm), and the junction depth is getting shallower and shallower, resulting in an instantaneous overvoltage when an ESD event occurs. The phenomenon (Electrical Overstress, referred to as EOS) will easily break ...

AI Technical Summary

Problems solved by technology

[0005] However, figure 1 The traditional R-C type power supply clamping circuit shown also has many disadvantages, such as: under the impact of ESD, the turn-on time of the discharge transistor 131 is too short, the leakage current is too large under the normal operation of the circuit, and the circuit Less robustness against false triggering, etc.

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