Nanowire array formation method

Abstract

The invention relates to a nanowire array formation method. The method comprises steps that 1, multiple mask patterns are formed on a substrate; 2, the multiple mask patterns are taken as masks, and the multi-period etching technology is carried out on the substrate to form multiple nanowires; 3, the multiple mask patterns are removed, wherein each etching period of the step 2 further comprises a1, the surface oxidation layer is removed; a2, a groove perpendicular to a side wall is formed through anisotropy etching; a3, the bottom portion and the side wall of the groove are oxidized to form temporary protection layers; a4, the temporary protection layer on the bottom portion of the groove is removed; a5, concave portions and protruding portions are formed through isotropy etching; and a6, surfaces of the concave portions and the protruding portions are oxidized. Through the method, etching gas combination is adjusted in each etching period, a nanowire array is formed through multi-period etching, the method is compatible with the CMOS technology in the prior art, the extra self-limit oxidation technology is not needed, cost is reduced, and efficiency is improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, and more specifically, to a method for forming a nanowire array. Background technique [0002] With the continuous shrinking of integrated circuit devices according to the requirements of Moore's Law and the demand for more advanced devices in the consumer market, the current advanced logic CMOS device technology has reached the 22nm node and is expected to enter the 14 / 16nm node on time. This poses a challenge to many process technologies, especially etching technology, because it forms the pattern of the device, especially the lines of the active area, making the manufacture of integrated circuits possible. Among them, etching to form nanowires used as source and drain regions and channel regions is a key technology of CMOS VLSI. In addition, the nanowire transistor using the three-dimensional stacked "gate all around" nanowire channel has ultra-low static power co...

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Problems solved by technology

However, the self-limiting oxidation process generally takes a long time, which affects the efficiency

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