Active components and high-voltage semiconductor components using them

Abstract

The invention discloses an active element and a high-voltage semiconductor element using the same. The high-voltage semiconductor element includes a substrate, a first well having a first conductive state and extending downward from the surface of the substrate, and a plurality of active elements connected to each other. They are formed on the substrate at a distance from each other, and adjacent active components are electrically insulated from each other through an insulator. An active component includes a diffusion region doped with impurities in a first conductivity state and extending downward from a surface of the first well, a ring-type gate formed in the diffusion region, and a light source having a second conductivity state. The doped region, the lightly doped region extends downward from a surface of the diffusion region. The lightly doped region is an edge deviated from the insulator.

Description

technical field [0001] The present invention relates to an active device and a high-voltage semiconductor device using the active device, and in particular to a device capable of supporting high-voltage operation without STI edge issue (free of STI edge issue) An active element and a high-voltage semiconductor element to which the active element is applied. Background technique [0002] In very large-scale integration (VLSI) technology, shallow trench isolation (shallow-trench isolation, STI) is usually used to isolate active components (such as complementary metal oxide semiconductor transistors) and define channel width. However, related researchers have found that STI edges can cause many serious problems for application components. [0003] figure 1 A conventional layout of a semiconductor device is shown. The semiconductor device includes a plurality of active devices 10 disposed on a substrate at a distance from each other, and all of them are located in a first we...

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Problems solved by technology

[0005] Generally speaking, there are several non-ideal conditions at the edge of the STI, such as: (1) Boron segregation occurs on the STI sidewall, resulting in p-well doping loss; (2) ) STI induced stress will affect the stability of the threshold voltage (Vt); and (3) some interface traps or dislocations will increase the leakage current

These conditions can cause sub-threshold characteristics and higher leakage current problems

Although, at present, a sidewall STI pocket implant is often applied to the "weak point" of the structure (such as figure 2 Selected in the middle circle) to increase the local well doping at the STI sidewall and suppress the double-hump leakage (curve Process-3), the structure still has disadvantages, including: (1) It will reduce the high voltage Junction breakdown of NMOS, as junction (lightly doped NM) sees more P-type well doping at STI edge, and (2) severe narrow channel width effect as channel width scales down (snarrow-width effect)

Therefore, STI sidewall pocket doping still affects the control of channel doping and threshold voltage

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