Thin film transistor and manufacturing method thereof, array substrate and display device

Abstract

The invention provides a film transistor and a manufacturing method thereof, and an array substrate and a display device. The film transistor comprises an active layer, an insulation layer arranged on the active layer, a first electrode layer and a second electrode layer, wherein the insulation layer comprises first through holes and a second through hole, the first through holes comprise a lower through hole close to the active layer and an upper through hole connected with the lower through hole, the smallest inner diameter of the upper through hole is greater than or equal to the largest inner diameter of the lower through hole, the first electrode layer is arranged in the upper through hole of the insulation layer, the first electrode is connected with the active layer through the lower through hole, and the second electrode layer is arranged on the insulation layer and is connected with the active layer through the second through hole. Through the film transistor and the manufacturing method thereof, and the array substrate and the display device, the product yield is improved.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a thin film transistor and a manufacturing method thereof, an array substrate and a display device. Background technique [0002] With the rapid development of the liquid crystal display industry, there is more and more pursuit of improvement in display performance, among which high-resolution display panels have gradually become one of the mainstream, so that consumers are not only concerned about the size and proportion of the display when purchasing the display. There are strict requirements, and there is already a benchmark for the resolution. With the improvement of the resolution of the display panel, the existing technology is increasingly challenging the technological limit. [0003] For details, see figure 1 , figure 1 A cross-sectional view of an array substrate 100 of a display panel in the prior art is shown. figure 1 The middle array substrate 100 includes a sub...

AI Technical Summary

Problems solved by technology

[0005] 1) Due to the increase of circuit integration, the trace widths D1 and D2 of the source electrode 122 and the drain electrode 125 are correspondingly reduced, and the process difficulty is increased. The risk of climbing and disconnection of vias on the inter-insulation layer 151;

[0006] 2) Due to the increase of circuit integration, the trace width D2 of the drain electrode 125 is correspondingly reduced, and the contact area between the pixel electrode 140 and the drain electrode 125 is reduced. Risk of line breaks in hole climbing; and

[0007] 3) Due to the increase of circuit integration, the distance D3 between the source electrode 122 and the drain electrode 125 is correspondingly reduced, the difficulty of the process increases, and the source electrode 122 and the drain electrode 125 are easily contacted and short-circuited, which affects the product yield

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