Measuring circuit and method for measuring data setup time of memory

Abstract

The invention discloses a measuring circuit for data establishing time of storage. The measuring circuit comprises a first D trigger, wherein an output data is sent to a data input end of the storage under the control of the first clock signal; a data output end of the storage is connected with the data input end of a second D trigger and is used for outputting under the control of a third clock signal; a second clock signal is connected with a clock input end of the storage; the third clock signal is connected with the clock input end of the second D trigger; multistage buffers are serially connected into a buffer serial circuit which is used for outputting the first, second and third clock signals and adjusting deviation values among the first, second and third clock signals; the data establishing time of the storage can be acquired by gradually approaching the magnitude setting of the deviation values of the first, second and third clock signals. The invention also discloses a measuring circuit for the data establishing time of the storage. According to the method provided by the invention, the measuring precision can be increased.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a measurement circuit for the data setup time (Setup) of a memory; the invention also relates to a method for measuring the data setup time of the memory. Background technique [0002] Such as figure 1 As shown, it is a schematic diagram of the data establishment time of the memory; the data input end of the memory is connected to the data input signal Data, and the clock input end is connected to the clock input signal CLK. On the rising edge of the clock input signal CLK, the output end of the memory outputs data. A condition for the memory to achieve correct output is that the data input signal Data must remain stable before a data setup time from the rising edge of the clock input signal CLK, and the signal that changes within the data setup time before the rising edge of the clock input signal CLK will not be output. [0003] exist figure 1 Among them, Set...

AI Technical Summary

Problems solved by technology

[0005] Existing test methods are affected by factors such as the machine, probe card, and test wiring, and the accuracy is not high enough

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